參數(shù)資料
型號(hào): ADT7408CCPZ2-R2
廠商: ANALOG DEVICES INC
元件分類: 溫度/濕度傳感器
英文描述: DIGITAL TEMP SENSOR-SERIAL, 12BIT(s), 4Cel, SQUARE, SURFACE MOUNT
封裝: 3 X 3 MM, MO-229VEED-4, LFCSP-8
文件頁(yè)數(shù): 7/22頁(yè)
文件大?。?/td> 570K
代理商: ADT7408CCPZ2-R2
Preliminary Technical Data
ADT7408
Rev. PrC | Page 15 of 22
ADT7408 SERIAL INTERFACE
Control of the ADT7408 is carried out via the SMBus-/I2C-
compatible serial interface. The ADT7408 is connected to this
bus as a slave and is under the control of a master device.
Figure shows a typical SMBus-/I2C- interface connection.
Figure 7. Typical SMBus/I2C Interface Connection
Serial Bus Address
Like all SMBus/-I2C- compatible devices, the ADT7408 has a 7-
bit serial address. The four MSBs of this address for the
ADT7408 are set to 0011. The three LSBs are set by Pin 1, Pin 2,
and Pin 3 (A0, A1 and A2). These pins can be configured either
low or high permanently or dynamically to give eight different
address options. Table 20 shows the different bus address
options available. Recommended pullup resistor value on the
SDA and SCL lines is 2.2k -10 k .
Table 20. SMBus/I2C Bus Address Options
BINARY
A6 A5 A4 A3 A2 A1 A0
HEX
0011 0 0 0
0011 0 0 1
0011 0 1 0
0011 0 1 1
0011 1 0 0
0011 1 0 1
0011 1 1 0
0011 1 1 1
0x24
0x25
0x26
0x27
0x28
0x29
0x30
0x31
The ADT7408 has been designed with a SMBus/I2C timeout.
The SMBus/I2C interface will timeout after 75 ms to 325 ms of
no activity on the SDA line. After this timeout the ADT7408
will reset the SDA line back to its idle state (SDA set to high
impedance) and wait for the next start condition.
The serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a start
condition, defined as a high to low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus a R/W bit. The R/W bit
determines whether data will be written to, or read from,
the slave device.
2.
The peripheral with the address corresponding to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the acknowledge bit. All other devices on the bus now
remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit is a 0 then the
master will write to the slave device. If the R/W bit is a 1
the master will read from the slave device.
3.
Data is sent over the serial bus in sequences of 9 clock
pulses, 8 bits of data followed by an acknowledge bit from
the receiver of data. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, as a low to high transition when
the clock is high may be interpreted as a STOP signal.
4.
When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master
will pull the data line high during the 10th clock pulse to
assert a STOP condition. In READ mode, the master
device will pull the data line high during the low period
before the 9th clock pulse. This is known as no
acknowledge. The master will then take the data line low
during the low period before the 10th clock pulse, then
high during the 10th clock pulse to assert a STOP
condition.
Any number of bytes of data may be transferred over the serial
bus in one operation. However, it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
The I2C address set up by the three address pins is not latched
by the device until after this address has been sent twice. On the
8th SCL cycle of the second valid communication, the serial bus
address is latched in. This is the SCL cycle directly after the
device has seen its own I2C serial bus address. Any subsequent
changes on this pin will have no affect on the I2C serial bus
address.
Event#
ADT7408
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