參數(shù)資料
型號: ADT7317ARQ
廠商: Analog Devices, Inc.
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:37; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:15-35
中文描述: SPI/I2C兼容,10位數(shù)字溫度傳感器和四DAC的電壓輸出12/10/8-Bit
文件頁數(shù): 4/32頁
文件大?。?/td> 340K
代理商: ADT7317ARQ
–4–
REV. PrN
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
DAC AC CHARACTERISTICS
1
(V
DD
= +2.7V to +5.5 V; R
L
=4k7
to GND; C
L
=200pF to GND;
4K7
to V
DD
; All specifications T
MIN
to T
MAX
unless otherwise noted.)
Typ @ 25°C
Max
Units
Conditions/Comments
Parameter
2
Min
Output Voltage Settling Time
ADT7318
ADT7317
ADT7316
V
REF
=V
DD
=+5V
1/4 Scale to 3/4 Scale change (40 Hex to C0 Hex)
1/4 Scale to 3/4 Scale change (100 Hex to 300 Hex)
1/4 Scale to 3/4 Scale change (400 Hex to
C00 Hex)
6
7
8
8
9
μs
μs
μs
10
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
0.7
12
0.5
1
0.5
3
200
-70
V/μs
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
1 LSB change around major carry.
V
REF
=2V±0.1Vpp
V
REF
=2.5V±0.1Vpp. Frequency=10kHz.
NOTES
1
Guaranteed by Design and Characterization, not production tested
2
See Terminology
Specifications subject to change without notice.
t
1
t
4
t
2
t
3
t
5
SCL
SDA
DATA IN
SDA
DATA OUT
Figure 1. Diagram for I
2
C Bus Timing
I
DD
(Normal Mode)
13
I
DD
(Power Down Mode)
0.85
1
0.5
tbd
tbd
1.3
3
1
tbd
tbd
mA
μA
μA
μW
μW
V
IH
= V
DD
and V
IL
= GND
V
DD
= +4.5V to +5.5V, V
IH
=V
DD
and V
IL
=GND
V
DD
= +2.7V to +3.6V, V
IH
=V
DD
and V
IL
=GND
V
DD
= +2.7 V. Using Normal Mode
V
DD
= +2.7 V. Using Shutdown Mode
Power Dissipation
tbd
tbd
Notes:
1
Temperature ranges are as follows: A Version: -40°C to +125°C.
2
See Terminology.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range:; ADT7316 (code 115 to 4095); ADT7317 (code 28 to 1023); ADT7318 (code 8 to 255)
5
See Terminology.
6
Guaranteed by Design and Characterization, not production tested
7
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
REF
=V
DD
,
"Offset plus Gain" Error must be positive.
8
The SDA & SCL timing is measured with the input filters turned on so as to meet the Fast-Mode I
2
C specification. Switching off the input filters improves the transfer
rate but has a negative affect on the EMC behaviour of the part.
9
Guaranteed by design. Not tested in production.
10
Guaranteed by design and characterization, not production tested.
11
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
12
Measured with the load circuit of Figure 3.
13
I
spec. is valid for all DAC codes. Interface inactive. All DACs active. Load currents excluded.
Specifications subject to change without notice.
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ADT7318 Circular Connector; No. of Contacts:37; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:15-35
ADT7318ARQ Circular Connector; No. of Contacts:37; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:15-35
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