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參數(shù)資料
| 型號： | ADSP-BF524KBCZ-4C2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CTRLR 400MHZ 289CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點(diǎn) |
| 接口： | DMA，I²C，PPI，SPI，SPORT，UART，USB |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | ROM（32 kB） |
| 芯片上RAM： | 132kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.30V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 289-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 289-CSPBGA（12x12） |
| 包裝： | 托盤 |
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Rev. A
|
Page 4 of 36
|
March 2010
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
To allow an external device to generate the central reference
clock, apply the external clock signal directly through the XTI/
CODEC_MCLK input pin. In this configuration, the oscillator
circuit of the codec can be powered down by using the OSCPD
bit (Register R6, Bit D5) to reduce power consumption.
To accommodate applications with very high frequency master
clocks, the internal core reference clock of the codec can be set
to either CODEC_MCLK or CODEC_MCLK divided by 2. This
is enabled by adjusting the setting of the CLKDIV2 bit (Register
R8, Bit D6). The CODEC_CLKOUT pin can also drive external
clock sources with either the codec clock signal or codec clock
divided by 2 by enabling the CLKODIV2 bit (Register R8,
Bit D7).
ADC AND DAC
The codec contains a pair of oversampling
Σ-Δ ADCs. The
maximum ADC full-scale input level is 1.0 Vrms when
AVDD = 3.3 V. If the input signal to the ADC exceeds this
level, data overloading occurs and causes audible distortion.
The ADC can accept analog audio input from either the stereo
line inputs or the monaural microphone input. Note that the
ADC can only accept input from a single source, so the pro-
grammer must choose either the line inputs or the microphone
input using the INSEL bit (Register R4, Bit D2). The digital data
from the ADC output, once converted, is processed using the
ADC filters.
Complementary to the
Σ-Δ ADC channels, the codec contains a
pair of oversampling DACs that convert the digital audio data
from the internal DAC filters into an analog audio signal. The
DAC output can also be muted by setting the DACMU bit (Reg-
ister R5, Bit D3) in the control register.
ADC HIGH-PASS AND DAC DE-EMPHASIS FILTERS
The ADC and DAC employ separate digital filters that perform
24-bit signal processing. The digital filters are used for both
record and playback modes and are optimized for each individ-
ual sampling rate used.
For recording mode operations, the unprocessed data from the
ADC enters the ADC filters and is converted to the appropriate
sampling frequency, then is output to the digital audio interface.
For playback mode operations, the DAC filters convert the digi-
tal audio interface data to oversampled data using a sampling
rate selected by the programmer. The oversampled data is pro-
cessed by the DAC and sent to the analog output mixer by
enabling the DACSEL (Register R4, Bit D4).
Programmers have the option of setting up the device so that
any dc offset in the input source signal is automatically detected
and removed. To accomplish this, enable the digital high-pass
filter (see Table 22 on Page 30 for characteristics) contained in
the ADC digital filters by using the ADCHPD bit (Register R5,
Bit D0).
In addition, programmers can implement digital de-emphasis
by using the DEEMPH bits (Register R5, Bit D1 and Bit D2).
ANALOG AUDIO INTERFACES
The codec includes stereo single-ended line inputs and a mon-
aural microphone input to the on-board ADC. Either the line
inputs or the microphone input, but not both simultaneously,
can be connected to the ADC by setting the INSEL bit (Register
R4, Bit D2).
The codec also includes line and headphone outputs from the
on-board DAC. The line or microphone inputs can be routed
and mixed directly to the output terminals.
Stereo Line and Monaural Microphone Inputs
The single-ended stereo line inputs (RLINEIN and LLINEIN)
are internally biased to VMID by way of a voltage divider
between AVDD and AGND (see Figure 2). The line input signal
can be connected to the internal ADC and, if desired, routed
directly to the outputs via the bypass path by using the BYPASS
bit (Register R4, Bit D3).
The line input volume can be adjusted from –34.5 dB to +33 dB
in steps of +1.5 dB by setting the LINVOL (Register R0, Bit D0
to Bit D5) and RINVOL (Register R1, Bit D0 to Bit D5) bits. By
default the volume is independently adjustable for both right
and left line inputs. However, if the LRINBOTH or RLINBOTH
bit is programmed, both LINVOL and RINVOL are loaded with
the same value. The programmer can also set the LINMUTE
(Register R0, Bit D7) and RINMUTE (Register R1, Bit D7) bits
to mute the line input signal to the ADC.
The high impedance, low capacitance monaural microphone
input pin (MICIN, shown in Figure 3 ) has two gain stages and a
microphone bias level (MICBIAS) that is internally biased to the
VMID voltage level by way of a voltage divider between AVDD
and AGND. The microphone input signal can be connected to
the internal ADC and, if desired, routed directly to the outputs
via the sidetone path by using the SIDETONE bit (Register R4,
Bit D5).
Figure 2. Line Input to ADC
ADC
OR
BYPASS
RLINEIN
or
LLINEIN
AVDD
VMID
AGND
+
–
INTERNAL CIRCUITRY
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-BF525 | 制造商:Analog Devices 功能描述: |
| ADSP-BF525ABCZ-5 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC ADSP-BF525 Processor 533Mhz Ethernet USB RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| ADSP-BF525ABCZ-6 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC ADSP-BF525 Processor 600Mhz Ethernet USB RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| ADSP-BF525BBCZ-5A | 功能描述:IC DSP CTRLR 16B 533MHZ 208BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF525KBCZ-5 | 功能描述:IC DSP CTRLR 16B 533MHZ 289BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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