參數(shù)資料
型號: ADSP-BF524KBCZ-3C2
廠商: Analog Devices Inc
文件頁數(shù): 1/36頁
文件大小: 0K
描述: IC DSP CTRLR 300MHZ 289CSPBGA
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: 定點
接口: DMA,I²C,PPI,SPI,SPORT,UART,USB
時鐘速率: 300MHz
非易失內(nèi)存: ROM(32 kB)
芯片上RAM: 132kB
電壓 - 輸入/輸出: 1.8V,2.5V,3.3V
電壓 - 核心: 1.30V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 289-LFBGA,CSPBGA
供應(yīng)商設(shè)備封裝: 289-CSPBGA(12x12)
包裝: 托盤
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Blackfin Embedded
Processor with Codec
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2010 Analog Devices, Inc. All rights reserved.
PROCESSOR FEATURES
Up to 600 MHz high performance Blackfin processor
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations. See operating conditions in the published
ADSP-BF52x processor data sheet.
Programmable on-chip voltage regulator (ADSP-BF523/
ADSP-BF525/ADSP-BF527processors only)
Embedded low power audio codec
289-ball (12 mm x 12 mm) CSP_BGA package
132K bytes of on-chip memory
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI and TWI
memory or from host devices including SPI, TWI, and UART
Code security with Lockbox Secure Technology
one-time-programmable (OTP) memory
Memory management unit providing memory protection
2 dual-channel memory DMA controllers
EMBEDDED CODEC FEATURES
Stereo, 24-bit ADCs and DACs
DAC SNR: 100 dB (A-weighted), THD: –80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: –80 dB at 48 kHz, 3.3 V
Highly efficient headphone amplifier
Stereo line input and monaural microphone input
Low power
7 mW stereo playback (1.8 V supply)
14 mW record and playback (1.8 V supply)
Low supply voltages
Analog: 1.8 V to 3.6 V
Digital core: 1.8 V min
Digital I/O: 1.8 V to 3.6 V
256 × fS /384 × fS oversampling rate in normal mode;
250 × fS/272 × fS oversampling rate in USB mode
Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,
and 96 kHz
PERIPHERALS
See the published ADSP-BF52x processor data sheet for
additional peripherals
SPORT0
TIMER0
VOLTAGE REGULATOR*
*REGULATOR AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS ONLY
PORT J
GPIO
PORT H
GPIO
PORT G
GPIO
PORT F
JTAG TEST AND EMULATION
PERIPHERAL
ACCESS BUS
OTP MEMORY
COUNTER
WATCHDOG TIMER
RTC
TWI
SPORT1
NFC
PPI
UART0
SPI
TIMER7-1
EMAC
HOST DMA
BOOT
ROM
DMA
ACCESS
BUS
INTERRUPT
CONTROLLER
DMA
CONTROLLER
L1 DATA
MEMORY
L1 INSTRUCTION
MEMORY
USB
16
DCB
EAB
EXTERNAL PORT
FLASH, SDRAM CONTROL
B
UART1
DEB
CODEC
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