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參數(shù)資料
| 型號： | ADSP-BF518BSWZ-4F4 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/68頁 |
| 文件大小： | 0K |
| 描述： | IC DSP 16/32B 400MHZ LP 176LQFP |
| 標準包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | 定點 |
| 接口： | 以太網(wǎng)，I²C，PPI，RSI，SPI，SPORT，UART/USART |
| 時鐘速率： | 400MHz |
| 非易失內(nèi)存： | 閃存（4Mb） |
| 芯片上RAM： | 116kB |
| 電壓 - 輸入/輸出： | 1.8V，2.5V，3.3V |
| 電壓 - 核心： | 1.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 176-LQFP 裸露焊盤 |
| 供應商設備封裝： | 176-LQFP-EP（24x24） |
| 包裝： | 托盤 |
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Rev. B
|
Page 19 of 68
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January 2011
Port J
PJ0:SCL
I/O 5V TWI Serial Clock (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I
2C specification for the proper resistor value.)
E
PJ1:SDA
I/O 5V TWI Serial Data (This signal is an open-drain output and requires a pull-up
resistor. Consult version 2.1 of the I
2C specification for the proper resistor value.)
E
Real Time Clock
RTXI
I
RTC Crystal Input (This ball should be pulled low when not used.)
RTXO
O
RTC Crystal Output (Does not three-state during hibernate)
JTAG Port
TCK
I
JTAG Clock
TDO
O
JTAG Serial Data Out
C
TDI
I
JTAG Serial Data In
TMS
I
JTAG Mode Select
TRST
I
JTAG Reset (This signal should be pulled low if the JTAG port is not used.)
EMU
O
Emulation Output
C
Clock
CLKIN
I
Clock/Crystal Input
XTAL
O
Crystal Output (If CLKBUF is enabled, does not three-state during hibernate)
CLKBUF
O
Buffered XTAL Output (If enabled, does not three-state during hibernate)
C
Mode Controls
RESET
I
Reset
NMI
I
Non-maskable Interrupt (This signal should be pulled high when not used.)
BMODE2-0
I
Boot Mode Strap 2-0
Voltage Regulation Interface
PG
I
Power Good (This signal should be pulled low when not used.)
EXT_WAKE
O
Wake up Indication (Does not three-state during hibernate)
C
Power Supplies
ALL SUPPLIES MUST BE POWERED See Operating Conditions on Page 20.
VDDEXT
PI/O Power Supply
VDDINT
P
Internal Power Supply
VDDRTC
P
Real Time Clock Power Supply
VDDFLASH
P
Internal SPI Flash Power Supply
VDDMEM
PMEM Power Supply
VPPOTP
P
OTP Programming Voltage
VDDOTP
POTP Power Supply
GND
G
Ground for All Supplies
1 See Output Drive Currents on Page 50 for more information about each driver type.
2 When driven low, the PF15 signal can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as PHYINT. If the pin/ball
is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the signal with a resistor.
3 Boot host wait is a GPIO signal toggled by the boot kernel. The mandatory external pull-up/pull-down resistor defines the signal polarity.
4 A pull-up resistor is required for the boot from external SPI EEPROM or flash (BMODE = 0x3).
Table 7. Signal Descriptions
Signal Name
Type Function
Driver
Type1
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