參數(shù)資料
型號: ADSP-21991BBC
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: SigmaDSP 28-/56-Bit Audio Processor with Two ADCs and Four DACs
中文描述: 16-BIT, 150 MHz, OTHER DSP, PBGA196
封裝: MINI, BGA-196
文件頁數(shù): 23/44頁
文件大?。?/td> 589K
代理商: ADSP-21991BBC
–23–
REV. 0
ADSP-21991
Clock In and Clock Out Cycle Timing
Table 5
and
Figure 6
describe clock and reset operations. Com-
binations of CLKIN and clock multipliers must not select
core/peripheral clocks in excess of 160 MHz/80 MHz for the
ADSP-21991BST and 150 MHz/75 MHz for the ADSP-
21991BBC, when the peripheral clock rate is one-half the core
clock rate. If the peripheral clock rate is equal to the core clock
rate, the maximum peripheral clock rate is 80 MHz for the
ADSP-21991BST and 75 MHz for the ADSP-21991BBC. The
peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512
HCLK cycles for the PLL to stabilize.
Table 5. Clock In and Clock Out Cycle Timing
Parameter
Timing Requirements
t
CK
t
CKL
t
CKH
t
WRST
t
MSS
t
MSH
t
MSD
t
PFD
Min
Max
Unit
CLKIN Period
1,
2
CLKIN Low Pulse
CLKIN High Pulse
RESET
Asserted Pulsewidth Low
MSELx/BYPASS Stable Before
RESET
Deasserted Setup
MSELx/BYPASS Stable After
RESET
Deasserted Hold
MSELx/BYPASS Stable After
RESET
Asserted
Flag Output Disable Time After
RESET
Asserted
10
4.5
4.5
200t
CLKOUT
40
1000
200
ns
ns
ns
ns
μs
ns
ns
ns
200
10
Switching Characteristics
t
CKOD
t
CKO
CLKOUT Delay from CLKIN
CLKOUT Period
3
0
12.5
5.8
ns
ns
1
In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), t
CK
= t
CCLK
.
2
In bypass mode, t
CK
= t
CCLK
.
3
CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.
Figure 6. Clock In and Clock Out Cycle Timing
t
CKOD
CLKOUT
MSEL6–0
BYPASS
DF
RESET
CLKIN
t
WRST
t
CKH
t
CK
t
CKL
t
MSH
t
CKO
t
PFD
t
MSD
t
MSS
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