Host Port ACC Mode Read Cycle Timing Table 18 and Figure 17 describe Host port read operations in Address Cycle Control " />
參數(shù)資料
型號： ADSP-2191MKCAZ-160
廠商： Analog Devices Inc
文件頁數(shù)： 25/48頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 144MBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SPI，SSP，UART
時鐘速率： 160MHz
非易失內(nèi)存： 外部
芯片上RAM： 160kB
電壓 - 輸入/輸出： 3.00V，3.30V
電壓 - 核心： 2.50V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 144-LFBGA
供應(yīng)商設(shè)備封裝： 144-迷你型BGA
包裝： 托盤
–31–
REV. A
ADSP-2191M
Host Port ACC Mode Read Cycle Timing
Table 18 and Figure 17 describe Host port read operations in
Address Cycle Control (ACC) mode. For more information on
ACK, Ready, ALE, and ACC mode selection, see the Host port
modes description on Page 8.
Table 18. Host Port ACC Mode Read Cycle Timing
Parameter
Min
Max
Unit
Switching Characteristics
t
RHKS1
HRD Asserted to HACK Asserted (ACK Mode) First Byte
12tHCLK
15t
HCLK +tNH
1
ns
t
RHKS2
HRD Asserted to HACK Asserted (Setup, ACK Mode)2
10
ns
t
RHKH
HRD Deasserted to HACK Deasserted (Hold, ACK Mode)
10
ns
t
RHS
HRD Asserted to HACK Asserted (Setup, Ready Mode)
10
ns
t
RHH
HRD Asserted to HACK Deasserted (Hold, Ready Mode)
First Byte
12tHCLK
15t
HCLK +tNH
1
ns
t
RDH
HRD Deasserted to Data Invalid (Hold)
1
ns
t
WSHKS
HWR Asserted to HACK Asserted (Setup) During Address
Latch
10
ns
t
WHHKH
HWR Deasserted to HACK Deasserted (Hold) During
Address Latch
10
ns
t
RDD
HRD Deasserted to Data Disable
10
ns
Timing Requirements
t
CSAL
HCMS or HCIOMS Asserted to HALE Asserted (Delay)
0ns
t
ALCS
HALE Deasserted to Optional
HCMS or HCIOMS
Deasserted
1ns
t
RCSW
HRD Deasserted to HCMS or HCIOMS Deasserted
0
ns
t
ALW
HALE Asserted to HWR Asserted
0.5
ns
t
ALER
HALE Deasserted to HWR Asserted
1
ns
t
CSR
HCMS or HCIOMS Asserted to HRD Asserted
0ns
t
RCS
HRD Deasserted (After Last Byte) to HCMS or
HCIOMS Deasserted (Ready for Next Read)
0ns
t
WAL
HWR Deasserted to HALE Deasserted (Delay)
2.5
ns
t
HKRD
HACK Asserted to
HRD Deasserted (Hold, ACK Mode)
1.5
ns
t
ADW
Address Valid to
HWR Deasserted (Setup)
2
ns
t
WAD
HWR Deasserted to Address Invalid (Hold)
1
ns
t
HKWAL
HACK Asserted to
HWR Deasserted (Hold) During Address
Latch2
2ns
1t
NH are peripheral bus latencies (n
tHCLK); these are internal DSP latencies related to the number of peripherals attempting to access DSP memory at
the same time.
2Measurement is for the second, third, or fourth byte of a host read transaction. The quantity of bytes to complete a host read transaction is dependent on
the data bus size (8 or 16 bits) and the data type (16 or 24 bits).
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