參數(shù)資料
型號(hào)： ADSP-2191MBSTZ-140
廠商： Analog Devices Inc
文件頁數(shù)： 35/48頁
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 144LQFP
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SPI，SSP，UART
時(shí)鐘速率： 140MHz
非易失內(nèi)存： 外部
芯片上RAM： 160kB
電壓 - 輸入/輸出： 3.00V，3.30V
電壓 - 核心： 2.50V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
其它名稱： ADSP-2191MBSTZ140
ADSP-2191M
–40–
REV. A
Output Drive Currents
Figure 25 shows typical I-V characteristics for the output drivers
of the ADSP-2191M. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Power Dissipation
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
Number of output pins that switch during each cycle (O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (V
DD)
and is calculated by the formula below.
The load capacitance includes the processor’s package capaci-
tance (C
IN). The switching frequency includes driving the load
high and then back low. Address and data pins can drive high and
low at a maximum rate of 1/(2t
CK). The write strobe can switch
every cycle at a frequency of 1/t
CK. Select pins switch at 1/(2tCK),
but selects can switch on each cycle. For example, estimate P
EXT
with the following assumptions:
A system with one bank of external data memory—asyn-
chronous RAM (16-bit)
One 64K 16 RAM chip is used with a load of 10 pF
Maximum peripheral speed CCLK = 80 MHz, HCLK =
80 MHz
External data memory writes occur every other cycle, a
rate of 1/(4t
HCLK), with 50% of the pins switching
The bus cycle time is 80 MHz (t
HCLK = 12.5 ns)
The P
EXT equation is calculated for each class of pins that can
drive as shown in Table 23.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with the
following formula.
Where:
P
EXT is from Table 23
P
INT is IDDINT
2.5 V, using the calculation I
DDINT listed
Note that the conditions causing a worst-case P
EXT are different
from those causing a worst-case P
INT. Maximum PINT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Test Conditions
The DSP is tested for output enable, disable, and hold time.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by –V is dependent on the capacitive load, C
L and the
load current, I
L. This decay time can be approximated by the
equation below.
Figure 25. Typical Drive Currents
SOURCE (VDDEXT)VOLTAGE – V
03.5
0.5
1.0
1.5
2.0
2.5
3.0
S
O
U
R
C
E
(V
D
E
X
T
)
C
U
R
E
N
T
–
m
A
–100
–80
–60
–40
–20
0
20
40
60
4.0
VDDEXT =3.3V @ +25°C
VDDEXT =3.0V@ +85°C
VOH
VOL
VDDEXT =3.0V @ +85°C
VDDEXT =3.3V @ +25°C
VDDEXT =3.65V @ – 40°C
INPUT CURRENT
OUTPUT CURRENT
VDDEXT = 3.65V @ –40°C
P
EXT
OC
×
V
DD
2
×
f
×
=
Table 23. P
EXT Calculation Example
Pin Type
# of Pins
% Switching
C
f
VDD2
= PEXT
Address
15
50
10 pF
20 MHz
10.9 V
= 0.01635 W
MSx
10
10 pF
20 MHz
10.9 V
= 0.0 W
WR
1—
10 pF
40 MHz
10.9 V
= 0.00436 W
Data
16
50
10 pF
20 MHz
10.9 V
= 0.01744 W
CLKOUT
1
—
10 pF
80 MHz
10.9 V
= 0.00872 W
P
EXT = 0.04687 W
P
TOTAL
P
=
EXT
P
INT
+
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