參數(shù)資料
型號(hào)： ADSP-2189NKSTZ-320
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 16-Bit, 80MIPS, 1.8V, 2 Serial Ports, Host Port, 192KB RAM; Package: 100 ld LQFP; No of Pins: 100; Temperature Range: Comm.
中文描述： 24-BIT, 40 MHz, OTHER DSP, PQFP100
封裝： LEAD FREE, MS-026BED, LQFP-100
文件頁(yè)數(shù)： 32/48頁(yè)
文件大小： 2334K
代理商： ADSP-2189NKSTZ-320
Rev. A
|
Page 38 of 48
|
August 2006
ADSP-218xN
IDMA Read, Short Read Cycle
Table 25. IDMA Read, Short Read Cycle
Parameter
1, 2
Min
Max
Unit
Timing Requirements:
tIKR
IACK Low Before Start of Read3
0ns
tIRP1
Duration of Read (DM/PM1)4
10
2tCK – 5
ns
tIRP2
Duration of Read (PM2)5
10
tCK – 5
ns
Switching Characteristics:
tIKHR
IACK High After Start of Read
10
ns
tIKDH
IAD15 – 0 Data Hold After End of Read
6
0ns
tIKDD
IAD15 – 0 Data Disabled After End of Read6
10
ns
tIRDE
IAD15 – 0 Previous Data Enabled After Start of Read
0
ns
tIRDV
IAD15 – 0 Previous Data Valid After Start of Read
10
ns
1 Short Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) Bit 14 of the IDMA overlay register, and is
disabled by default upon reset.
2 Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies.
3 Start of Read = IS Low and IRD Low.
4 DM Read or first half of PM Read.
5 Second half of PM Read.
6 End of Read = IS High or IRD High.
Figure 36. IDMA Read, Short Read Cycle
tIRP
tIKR
PREVIOUS
DATA
tIKHR
tIRDV
tIKDD
tIRDE
tIKDH
IAD15–0
IACK
IS
IRD
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