參數(shù)資料
型號(hào)： ADSP-2189NKST-320
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： 24-BIT, 40 MHz, OTHER DSP, PQFP100
封裝： MS-026BED, LQFP-100
文件頁數(shù)： 4/32頁
文件大?。?/td> 244K
代理商： ADSP-2189NKST-320
REV. A
ADSP-2189M
–
4
–
functionality is reconfigurable, the default state is shown in plain
text; alternate functionality is shown in italics.
Common-Mode Pins
Pin
# of
Name(s)
Pins I/O Function
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2
1
1
1
1
1
1
1
1
1
1
1
1
I
I
O
O
O
O
O
O
O
O
O
I
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt
Requests
1
I/O Programmable I/O Pin.
I
Level-Sensitive Interrupt Requests
1
I/O Programmable I/O Pin
I
Level-Sensitive Interrupt Requests
1
I/O Programmable I/O Pin
I
Edge-Sensitive Interrupt Requests
1
I/O Programmable I/O Pin
I
Mode Select Input—Checked Only
During
RESET
I/O Programmable I/O Pin During
Normal Operation
I
Mode Select Input—Checked Only
During
RESET
I/O Programmable I/O Pin During
Normal Operation
I
Mode Select Input—Checked
Only During
RESET
I/O Programmable I/O Pin During
Normal Operation
I
Mode Select Input—Checked Only
During
RESET
I/O Programmable I/O Pin During
Normal Operation
I
Clock or Quartz Crystal Input
O
Processor Clock Output
I/O Serial Port I/O Pins
I/O Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out
2
I
Power-Down Control Input
O
Power-Down Control Output
O
Output Flags
I
Internal VDD (2.5 V) Power
I
External VDD (2.5 V or 3.3 V)
Power
I
Ground
I/O For Emulation Use
PF7
IRQL1
PF6
IRQL0
PF5
IRQE
PF4
Mode D
1
1
1
1
PF3
Mode C
1
PF2
Mode B
1
PF1
Mode A
1
PF0
CLKIN, XTAL 2
CLKOUT
SPORT0
SPORT1
IRQ1:0
,
FI
,
FO
1
5
5
PWD
PWDACK
FL0, FL1, FL2 3
V
DDINT
V
DDEXT
1
1
2
4
GND
EZ-Port
10
9
NOTES
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, then the DSP will vector to the appropri-
ate interrupt vector address when the pin is asserted, either by external devices,
or set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Soft-
ware configurable.
Memory Interface Pins
The ADSP-2189M processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during
RESET
and cannot be changed while
the processor is running.
Full Memory Mode Pins (Mode C = 0)
Pin
# of
Name
Pins
I/O
Function
A13:0
14
O
Address Output Pins for Program,
Data, Byte and I/O Spaces
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses.)
D23:0
24
I/O
Host Mode Pins (Mode C = 1)
Pin
# of
Name
Pins
I/O
Function
IAD15:0
A0
16
1
I/O
O
IDMA Port Address/Data Bus
Address Pin for External I/O,
Program, Data, or Byte Access
1
Data I/O Pins for Program, Data
Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Config-
urable in Mode D; Open Drain
D23:8
16
I/O
IWR
IRD
IAL
IS
IACK
1
1
1
1
1
I
I
I
I
O
NOTE
1
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS
,
PMS
,
DMS
and
IOMS
signals.
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2189M provides four dedicated external interrupt
input pins,
IRQ2
,
IRQL0
,
IRQL1
and
IRQE
(shared with the
PF7:4 pins). In addition, SPORT1 may be reconfigured for
IRQ0
,
IRQ1
, FLAG_IN and FLAG_OUT, for a total of six
external interrupts. The ADSP-2189M also supports internal
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. The inter-
rupt levels are internally prioritized and individually maskable
(except power-down and reset). The
IRQ2
,
IRQ0
and
IRQ1
input pins can be programmed to be either level- or edge-sensi-
tive.
IRQL0
and
IRQL1
are level-sensitive and
IRQE
is edge-
sensitive. The priorities and vector addresses of all interrupts are
shown in Table I.
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