參數(shù)資料
型號(hào)： ADSP-2189NBSTZ-320
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： 16-Bit, 80MIPS, 1.8V, 2 Serial Ports, Host Port, 192KB RAM; Package: 100 ld LQFP; No of Pins: 100; Temperature Range: Ind
中文描述： 24-BIT, 40 MHz, OTHER DSP, PQFP100
封裝： LEAD FREE, MS-026BED, LQFP-100
文件頁(yè)數(shù)： 33/48頁(yè)
文件大?。?/td> 2334K
代理商： ADSP-2189NBSTZ-320
ADSP-218xN
Rev. A
|
Page 39 of 48
|
August 2006
IDMA Read, Short Read Cycle in Short Read Only Mode
Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode
Parameter
1
Min
Max
Unit
Timing Requirements:
tIKR
IACK Low Before Start of Read2
0ns
tIRP
Duration of Read3
10
ns
Switching Characteristics:
tIKHR
IACK High After Start of Read
10
ns
tIKDH
IAD15 – 0 Previous Data Hold After End of Read
0ns
tIKDD
IAD15 – 0 Previous Data Disabled After End of Read
10
ns
tIRDE
IAD15 – 0 Previous Data Enabled After Start of Read
0
ns
tIRDV
IAD15 – 0 Previous Data Valid After Start of Read
10
ns
1 Short Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register
or by an external host writing to the register. Disabled by default.
2 Start of Read = IS Low and IRD Low. Previous data remains until end of read.
3 End of Read = IS High or IRD High.
Figure 37. IDMA Read, Short Read Cycle in Short Read Only Mode
tIRP
tIKR
PR E V IO U S
DATA
tIKHR
tIR DV
tIKDD
tIRDE
tIKDH
IAD15–0
IA CK
IS
IRD
LEG EN D :
IM PL IES TH A T
IS AND IR D CAN BE
H E LD INDE FINITE LY BY HO S T
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