參數(shù)資料
型號(hào)： ADSP-2166
廠商： Analog Devices, Inc.
元件分類(lèi)： 基準(zhǔn)電壓源/電流源
英文描述： Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
中文描述： 無(wú)電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù)
文件頁(yè)數(shù)： 9/39頁(yè)
文件大?。?/td> 243K
代理商： ADSP-2166
REV. 0
ADSP-216x
–9–
Bus Interface
The ADSP-216x processors can relinquish control of their data
and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (
BR
). If the ADSP-216x is not performing an external
memory access, it responds to the active
BR
input in the next
cycle by:
Three-stating the data and address buses and the PMS,
DMS
,
BMS
,
RD
,
WR
output drivers,
Asserting the bus grant (BG) signal, and halting program
execution.
If the Go mode is set, however, the ADSP-216x will not halt
program execution until it encounters an instruction that
requires an external memory access.
If the ADSP-216x is performing an external memory access
when the external device asserts the
BR
signal, it will not three-
state the memory interfaces or assert the
BG
signal until the
cycle after the access completes (up to eight cycles later depend-
ing on the number of wait states). The instruction does not need
to be completed when the bus is granted; the ADSP-21xx will
grant the bus between two memory accesses if an instruction
requires more than one external memory access.
When the
BR
signal is released, the processor releases the
BG
signal, re-enables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when
RESET
is active. If this feature is
not used, the
BR
input should be tied high (to V
DD
).
POWER-DOWN
The ADSP-2165/ADSP-2166 processors have a low power
feature that lets the processor enter a very low power dormant
state through hardware or software control. A list of power-
down features follows:
Processor registers and on-chip memory contents are main-
tained during power-down.
Power-down mode holds the processor in CMOS standby
with a maximum current of less than 100
μ
A in some modes.
Support for an externally generated TTL or CMOS proces-
sor clock. The external clock can continue running during
power-down without affecting the lowest power rating.
Support for crystal operation includes disabling the oscillator
to save power. (The processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabilize).
When power-down mode is enabled, powering down of the
processor can be initiated either by externally generated
IRQ2
interrupt or by using the
IRQ2
force bit in the IFC
register.
Power-Down Acknowledge Pin (PWDACK) indicates when
the processor has entered power-down.
Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down.
Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
Low-to-high transition of the power-down flag input pin
(PWDFLAG) can be used to terminate power-down.
The
RESET
pin also can also be used to terminate
power-down.
Power-Down Control
Several parameters of power-down operation can be controlled
through control bits of the “power-down/sportl autobuffer con-
trol register.” This control register is memory-mapped at loca-
tion 0x3FEF and the power-down control bits are as follows:
bit[15] xtal: xtal pin disable during power-down
1 = disabled, 0 = enable (default)
bit[14] pwdflag: (read only )
when pwdena = 1, the value of bit [14] pwdflag is equal to the
status of the pwdflag input pin.
when pwdena = 0, the value of bit [14] pwdflag is equal to 0.
bit[13] pwdena: power-down enable
1 = enable, 0 = disable (default)
if pwdena is set to 0, then the output pin PWDACK is driven
low and the input pin PWDFLAG is disabled
Note: It is not recommended that power-down enable be set or
cleared during an
IRQ2
interrupt.
bit[12] pucr: power-up context reset
1 = soft reset, 0 = resume execution (default)
Entering Power-Down
The power-down sequence is defined as follows:
Enable power-down logic by setting the pwdena bit in the
power-down/sportl autobuffer control register.
Note: In order to power-down, the PWDENA bit must be set
before the
IRQ2
interrupt is initiated.
Initiate the power-down sequence by generating an
IRQ2
interrupt either externally or by software use of the IFC
register.
The processor vectors to the
IRQ2
interrupt vector located at
0x0004.
Any number of housekeeping instructions, starting at loca-
tion 0x0004 can be executed prior to the processor entering
the power-down mode.
The processor enters the power-down mode when the pro-
cessor executes an IDLE instruction while executing the
IRQ2
interrupt routine.
Notes:
If an RTI instruction is executed before the processor en-
counter an IDLE instruction, then the processor returns
from the
IRQ2
interrupt and the power-down sequence is
aborted.
The user can differentiate between a “normal”
IRQ2
inter-
rupt and a “power-down”
IRQ2
interrupt by resetting the
PWDFLAG pin and checking the status of this pin by testing
the PWDFLAG bit in the power-down/SPORT1 autobuffer
control register located at DM[0x3FEF].
相關(guān)PDF資料
PDF描述
ADSP-216X DSP Microcomputers with ROM
ADSP-2161BP-66 DSP Microcomputers with ROM
ADSP-2162BS-40 ADSP-2100 Family DSP Microcomputers
ADSP-2162KP-40 DSP Microcomputers with ROM
ADSP-2164KP-40 DSP Microcomputers with ROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-2166BS-52 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:DSP Microcomputers with ROM
ADSP-2166BS-66 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:DSP Microcomputers with ROM
ADSP-2166KS-52 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:DSP Microcomputers with ROM
ADSP-2166KS-66 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:DSP Microcomputers with ROM
ADSP-216X 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:DSP Microcomputers with ROM
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