參數(shù)資料
型號： ADSP-2165KS-100
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： DSP Microcomputers with ROM
中文描述： 24-BIT, 25 MHz, OTHER DSP, PQFP80
封裝： PLASTIC, MQFP-80
文件頁數(shù)： 24/39頁
文件大?。?/td> 243K
代理商： ADSP-2165KS-100
REV. 0
ADSP-216x
–24–
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
BUS REQUEST/BUS GRANT
16.67 MHz
Min
20 MHz
Min
25 MHz
Min
Frequency Dependency
Min
Parameter
Max
Max
Max
Max
Unit
Timing Requirements:
t
BH
BR
Hold After CLKOUT High
1
t
BS
BR
Setup Before CLKOUT Low
1
Switching Characteristics:
t
SD
CLKOUT High to
DMS
,
PMS
,
BMS
,
RD
,
WR
Disable
t
SDB
DMS
,
PMS
,
BMS
,
RD
,
WR
Disable to
BG
Low
t
SE
BG
High to
DMS
,
PMS
,
BMS
,
RD
,
WR
Enable
t
SEC
DMS
,
PMS
,
BMS
,
RD
,
WR
Enable to CLKOUT High
20
35
17.5
32.5
15
30
0.25t
CK
+ 5
0.25t
CK
+ 20
ns
ns
35
32.5
30
0.25t
CK
+ 20
ns
0
0
0
0
ns
0
0
0
0
ns
5
2.5
1.5
2
0.25t
CK
– 10
2
ns
NOTES
1
If
BR
meets the t
and t
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle.
BR
requires
a pulsewidth greater than 10 ns.
2
For 25 MHz only, the minimum frequency dependency formula for t
SEC
= (0.25t
CK
– 8.5).
Section 10.2.4, “Bus Request/Grant,” on page 212 of the
ADSP-2100 Family User’s Manual
, Third Edition,
states that “When
BR
is recognized, the processor responds
immediately by asserting
BG
during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors:
BG
is asserted in the cycle
after
BR
is
recognized. No external synchronization circuit is needed when
BR
is generated as an asynchronous signal.
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
t
BS
BR
t
BH
CLKOUT
PMS
,
DMS
BMS
,
RD
WR
BG
Figure 23. Bus Request/Bus Grant
相關(guān)PDF資料
PDF描述
ADSP-2165KS-80 DSP Microcomputers with ROM
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ADSP-2171BS-133 DSP Microcomputer
ADSP-2173BST-80 DSP Microcomputer
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