參數(shù)資料
型號(hào)： ADSP-2163KS-66
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputers with ROM
中文描述： 24-BIT, 16.67 MHz, OTHER DSP, PQFP80
封裝： METRIC, PLASTIC, QFP-80
文件頁(yè)數(shù)： 15/39頁(yè)
文件大小： 243K
代理商： ADSP-2163KS-66
REV. 0
ADSP-216x
–15–
POWER DISSIPATION EXAMPLE
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C
×
V
DD
2
×
f
C
= load capacitance,
f
= output switching frequency.
Example:
In an ADSP-2161 application where external data memory is
used and no other outputs are active, power dissipation is calcu-
lated as follows:
Assumptions:
External data memory is accessed every cycle with 50% of
the address pins switching.
External data memory writes occur every other cycle with
50% of the data pins switching.
Each address and data pin has a 10 pF total load at the pin.
The application operates at V
DD
= 5.0 V and t
CK
= 50 ns.
Total Power Dissipation
=
P
INT
+
(C
×
V
DD2
×
f
)
P
INT
= internal power dissipation (from Figure 9).
(
C
×
V
DD2
×
f
) is calculated for each output:
# of
Pins
Output
3
C
×
10 pF
×
10 pF
×
10 pF
×
10 pF
3
V
DD2
3
f
×
5
2
V
×
5
2
V
×
5
2
V
×
5
2
V
Address,
DMS
8
Data,
WR
RD
CLKOUT
×
20 MHz =40.0 mW
×
10 MHz =22.5 mW
×
10 MHz = 2.5 mW
×
20 MHz = 5.0 mW
9
1
1
70.0 mW
Total power dissipation for this example = P
INT
+ 70.0 mW.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
T
AMB
= T
CASE
– (PD
×
θ
CA
)
T
CASE
= Case Temperature in
°
C
PD = Power Dissipation in W
θ
CA
= Thermal Resistance (Case-to-Ambient)
θ
JA
= Thermal Resistance (Junction-to-Ambient)
θ
JC
= Thermal Resistance (Junction-to-Case)
Package
PLCC
MQFP
u
JA
27
°
C/W
60
°
C/W
u
JC
16
°
C/W
18
°
C/W
u
CA
11
°
C/W
42
°
C/W
CAPACITIVE LOADING
Figures 10 and 11 show capacitive loading characteristics for the
ADSP-2161/ADSP-2163/ADSP-2165.
C
L
– pF
R
00
175
25
50
150
1
V
DD
= 4.5V
8
6
4
100
125
75
7
5
3
2
Figure 10. Typical Output Rise Time vs. Load Capacitance, C
L
(at Maximum Ambient Operating Temperature)
C
L
– pF
–30
175
25
50
150
V
DD
= 4.5V
5
3
1
100
125
75
4
2
–2
–1
0
V
Figure 11. Typical Output Valid Delay or Hold vs. Load
Capacitance, C
L
(at Maximum Ambient Operating
Temperature)
ADSP-2161/ADSP-2163/ADSP-2165
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-2163KS-662 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers
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