參數(shù)資料
型號(hào)： ADSP-21366SKSQZENG
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝： LEAD FREE, MS-026BFB-HD, HSLQFP-144
文件頁數(shù)： 15/54頁
文件大?。?/td> 559K
代理商： ADSP-21366SKSQZENG
ADSP-21365/6
Preliminary Technical Data
Rev. PrA
|
Page 15 of 54
|
September 2004
ADSP-21365/6 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
Parameter
1
1
Specifications subject to change without notice.
2
Applies to input and bidirectional pins: AD15–0, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.
3
Applies to input pin CLKIN.
4
See
Thermal Characteristics on page 44
for information on thermal specifications.
5
See Engineer-to-Engineer Note (No. TBD) for further information.
K Grade
B Grade
C Grade
Min
Max
Min
Max
Min
Max
Unit
V
DDINT
Internal (Core) Supply Voltage
1.14
1.26
1.14
1.26
0.95
1.05
V
A
VDD
Analog (PLL) Supply Voltage
1.14
1.26
1.14
1.26
0.95
1.05
V
V
DDEXT
V
IH
2
V
IL
2
V
IH_CLKIN
3
External (I/O) Supply Voltage
3.13
3.47
3.13
3.47
3.13
3.47
V
High Level Input Voltage @ V
DDEXT
= max
2.0
V
DDEXT
+ 0.5
2.0
V
DDEXT
+ 0.5
2.0
V
DDEXT
+ 0.5
V
Low Level Input Voltage @ V
DDEXT
= min
–0.5
+0.8
–0.5
+0.8
–0.5
+0.8
V
High Level Input Voltage @ V
DDEXT
= max
1.74
V
DDEXT
+ 0.5
1.74
V
DDEXT
+ 0.5
1.74
V
DDEXT
+ 0.5
V
V
IL_CLKIN
T
AMB
4,
5
Low Level Input Voltage @ V
DDEXT
= min
–0.5
+1.19
–0.5
+1.19
–0.5
+1.19
V
Ambient Operating Temperature
0
+70
–40
+85
–40
+105
°
C
Parameter
1
V
OH
2
V
OL
2
I
IH
4, 5
I
IL
4
I
ILPU
5
I
OZH
6, 7
I
OZL
6
I
OZLPU
7
I
DD-INTYP
8, 9
AI
DD
10
C
IN
11,
12
1
Specifications subject to change without notice.
2
Applies to output and bidirectional pins: AD15–0, RD, WR, ALE, FLAG3–0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.
3
See
Output Drive Currents on page 43
for typical drive current capabilities.
4
Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.
5
Applies to input pins with 22.5 k
internal pullups: TRST, TMS, TDI.
6
Applies to three-statable pins: FLAG3–0.
7
Applies to three-statable pins with 22.5 k
pullups: AD15–0, DAI_Px, SPICLK, EMU, MISO, MOSI.
8
Typical internal current data reflects nominal operating conditions.
9
See Engineer-to-Engineer Note (No. TBD) for further information.
10
Characterized, but not tested.
11
Applies to all signal pins.
12
Guaranteed, but not tested.
Test Conditions
@ V
DDEXT
= min, I
OH
= –1.0 mA
3
@ V
DDEXT
= min, I
OL
= 1.0 mA
3
@ V
DDEXT
= max, V
IN
= V
DDEXT
max
@ V
DDEXT
= max, V
IN
= 0 V
@ V
DDEXT
= max, V
IN
= 0 V
@ V
DDEXT
= max, V
IN
= V
DDEXT
max
@ V
DDEXT
= max, V
IN
= 0 V
@ V
DDEXT
= max, V
IN
= 0 V
t
CCLK
= min, V
DDINT
= nom
A
VDD
= max
f
IN
=1 MHz, T
CASE
=25°C, V
IN
=1.2V
Min
2.4
Max
Unit
V
V
μA
μA
μA
μA
μA
μA
mA
mA
pF
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
Low Level Input Current Pullup
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current Pullup
Supply Current (Internal)
Supply Current (Analog)
Input Capacitance
0.4
10
10
200
10
10
200
500
10
4.7
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