參數(shù)資料
型號： ADSP-21365SKBC-ENG
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, MBGA-136
文件頁數(shù)： 36/54頁
文件大小： 559K
代理商： ADSP-21365SKBC-ENG
Rev. PrA
|
Page 36 of 54
|
September 2004
ADSP-21365/6
Preliminary Technical Data
SPDIF Transmitter
Serial data input to the SPDIF transmitter can be formatted as
left justified, I
2
S or right justified with word widths of 16, 18, 20,
or 24 bits. The following sections provide timing for the
transmitter.
SPDIF Transmitter—Serial Input Waveforms
Figure 27
shows the right-justified mode. LRCLK is HI for the
left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
Figure 28
shows the default I2S-justified mode. LRCLK is LO
for the left channel and HI for the right channel. Data is valid on
the rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.
Figure 29
shows the left-justified mode. LRCLK is HI for the left
channel and LO for the right channel. Data is valid on the rising
edge of SCLK. The MSB is left-justified to an LRCLK transition
with no MSB delay.
Figure 27. Right-Justified Mode
LRCLK
SCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB-1
MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
LSB
MSB
Figure 28. I
2
S-Justified Mode
MSB-1
MSB-2
LSB+2 LSB+1
LSB
LRCLK
SCLK
SDATA
LEFTCHANNEL
RIGHTCHANNEL
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB
Figure 29. Left-Justified Mode
LRCLK
SCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB+1
MSB
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相關代理商/技術參數(shù)
參數(shù)描述
ADSP-21365SKBCZENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21365SKSQ-ENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21365SKSQZENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21365YSWZ-2AA 功能描述:IC DSP 32BIT 200MHZ EPAD 144LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21365YSWZ-2BA 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit/40-Bit 200MHz 200MIPS 144-Pin LQFP EP
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