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參數(shù)資料
| 型號(hào)： | ADSP-21365SBBC-ENG |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, MBGA-136 |
| 文件頁數(shù)： | 6/54頁 |
| 文件大?。?/td> | 559K |
| 代理商： | ADSP-21365SBBC-ENG |
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Rev. PrA
|
Page 6 of 54
|
September 2004
ADSP-21365/6
Preliminary Technical Data
Using the DM bus and PM buses, with one bus dedicated to
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.
DMA Controller
The ADSP-21365/6’s on-chip DMA controller allows data
transfers without processor intervention. The DMA controller
operates independently and invisibly to the processor core,
allowing DMA operations to occur while the core is simulta-
neously executing its program instructions. DMA transfers can
occur between the ADSP-21365/6’s internal memory and its
serial ports, the SPI-compatible (Serial Peripheral Interface)
ports, the IDP (Input Data Port), the Parallel Data Acquisition
Port (PDAP) or the parallel port. Twenty-five channels of DMA
are available on the ADSP-21365/6—two for the SPI interface,
twelve via the serial ports, eight via the Input Data Port, two for
DTCP (or memory-to-memory data transfer when DTCP is not
used), and one via the processor’s parallel port. Programs can be
downloaded to the ADSP-21365/6 using DMA transfers. Other
DMA features include interrupt generation upon completion of
DMA transfers, and DMA chaining for automatic linked DMA
transfers.
Digital Audio Interface (DAI)
The Digital Audio Interface (DAI) provides the ability to con-
nect various peripherals to any of the DSPs DAI pins
(DAI_P20–1).
Programs make these connections using the Signal Routing
Unit (SRU, shown in
Figure 3
).
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon-
figurable signal paths.
The DAI also includes six serial ports, an S/PDIF receiver/trans-
mitter, a DTCP cipher (ADSP-21365 only), a precision clock
generator (PCG), eight channels of asynchronous sample rate
converters, an input data port (IDP), an SPI port, six flag out-
puts and six flag inputs, and three timers. The IDP provides an
additional input path to the ADSP-21365/6 core, configurable
as either eight channels of I
2
S serial data or as seven channels
plus a single 20-bit wide synchronous parallel data acquisition
port. Each data channel has its own DMA channel that is inde-
pendent from the ADSP-21365/6's serial ports.
For complete information on using the DAI, see the
ADSP-
2136x SHARC Processor Hardware Reference
.
Serial Ports
The ADSP-21365/6 features six synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog devices AD183x
family of audio codecs, ADCs, and DACs. The serial ports are
made up of two data lines, a clock and frame sync. The data
lines can be programmed to either transmit or receive and each
data line has a dedicated DMA channel.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTS are enabled,
or six full duplex TDM streams of 128 channels per frame.
The serial ports operate at a maximum data rate of 50M bits/s.
Serial port data can be automatically transferred to and from
on-chip memory via dedicated DMA channels. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig-
nals while the other SPORT provides the two receive signals.
The frame sync and clock are shared.
Serial ports operate in four modes:
Standard DSP serial mode
Multichannel (TDM) mode
I
2
S mode
Left-justified sample pair mode
Figure 3. ADSP-21365/6 I/O Processor and Peripherals Block Diagram
16
3
PRECISION CLOCK
GENERATORS (2)
SPI PORT (1)
4
SERIAL PORTS (6)
INPUT
DATA PORTS (8)
TIMERS (3)
3
DMA CONTROLLER
25 CHANNELS
I
(
C
PARALLEL PORT
4
GPIO FLAGS/IRQ/TIMEXP
S
ADDRESS/DATA BUS/ GPIO
CONTROL/GPIO
DIGITAL AUDIO INTERFACE
TO PROCESSOR BUSES AND
SYSTEM MEMORY
IO ADDRESS
BUS (18)
SRC (8 CHANNELS)
SPDIF (RX/TX)
DTCP CIPHER
PWM (16)
IO DATA
BUS (32)
SPI PORT (1)
4
20
I/O PROCESSOR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21365SBBCZENG | SHARC Processor |
| ADSP-21365SBSQ-ENG | SHARC Processor |
| ADSP-21365SKBCZENG | SHARC Processor |
| ADSP-21365SKSQZENG | SHARC Processor |
| ADSP-21366SKBCZENG | SHARC Processor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21365SBBCZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SBSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SBSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SCSQ-ENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
| ADSP-21365SCSQZENG | 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor |
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