參數(shù)資料
型號(hào)： ADSP-21364SBSQZENG
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PQFP144
封裝： LEAD FREE, MS-026BFB-HD, HSLQFP-144
文件頁數(shù)： 9/52頁
文件大?。?/td> 853K
代理商： ADSP-21364SBSQZENG
ADSP-21364
Preliminary Technical Data
Rev. PrB
|
Page 9 of 52
|
September 2004
Set conditional breakpoints on registers, memory,
and stacks
Trace instruction execution
Perform linear or statistical profiling of program execution
Fill, dump, and graphically plot the contents of memory
Perform source level debugging
Create custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel-
opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:
Control how the development tools process inputs and
generate outputs
Maintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices’ technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applica-
tions. Download components from the Web and drop them into
the application. Publish component archives from within Visu-
alDSP++. VCSE supports component implementation in
C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the processor or external memory with the
drag of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Defi-
nition File (LDF), allowing the developer to move between the
graphical and textual environments.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board(Target)
The Analog Devices family of emulators are tools that every
developer needs to test and debug hardware and software sys-
tems. Analog Devices has supplied an IEEE 1149.1 JTAG Test
Access Port (TAP) on each JTAG DSP. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea-
tures of the processor, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The processor must be halted to send data and com-
mands, but once an operation has been completed by the
emulator, the processor system is set running at full speed with
no impact on system timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the
EE-68: Analog Devices JTAG Emulation Technical
Reference
www.analog.com
to keep pace with improvements to emulator support.
相關(guān)PDF資料
PDF描述
ADSP-21364SCSQ-ENG SHARC Processor
ADSP-21364SCSQZENG SHARC Processor
ADSP-21364SKBC-ENG SHARC Processor
ADSP-21364SKBCZENG SHARC Processor
ADSP-21364SKSQ-ENG SHARC Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21364SCSQ-ENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21364SCSQZENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21364SKBC-ENG 制造商:Analog Devices 功能描述:
ADSP-21364SKBCZENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
ADSP-21364SKSQ-ENG 制造商:AD 制造商全稱:Analog Devices 功能描述:SHARC Processor
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。