參數(shù)資料
型號(hào)： ADSP-21266SKBCZ-2D
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： SHARC Embedded Processor
中文描述： 16-BIT, 66.67 MHz, OTHER DSP, PBGA136
封裝： ROHS COMPLIANT, MO-205AE, BGA-136
文件頁(yè)數(shù)： 4/44頁(yè)
文件大?。?/td> 426K
代理商： ADSP-21266SKBCZ-2D
Rev. B
|
Page 4 of 44
|
May 2005
ADSP-21266
GENERAL DESCRIPTION
The ADSP-21266 SHARC DSP is a member of the SIMD
SHARC family of DSPs featuring Analog Devices Super Har-
vard Architecture. The ADSP-21266 is source code compatible
with the ADSP-2126x, ADSP-21160, and ADSP-21161 DSPs as
well as with first generation ADSP-2106x SHARC processors in
SISD (single-instruction, single-data) mode. Like other SHARC
DSPs, the ADSP-21266 is a 32-bit/40-bit floating-point proces-
sor optimized for high performance audio applications with its
dual-ported on-chip SRAM, mask-programmable ROM, multi-
ple internal buses to eliminate I/O bottlenecks, and an
innovative digital audio interface.
As shown in the Functional Block Diagram on Page 1, the
ADSP-21266 uses two computational units to deliver a 5 to 10
times performance increase over previous SHARC processors
on a range of DSP algorithms. Fabricated in a state-of-the-art,
high speed, CMOS process, the ADSP-21266 DSP achieves an
instruction cycle time of 5 ns at 200 MHz or 6.6 ns at 150 MHz.
With its SIMD computational hardware, the ADSP-21266 can
perform 1200 MFLOPS running at 200 MHz, or 900 MFLOPS
running at 150 MHz.
Table 1
shows performance benchmarks for the ADSP-21266.
The ADSP-21266 continues SHARC’s industry-leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 2M bit dual-ported SRAM memory, 4M bit
dual-ported ROM, an I/O processor that supports 22 DMA
channels, six serial ports, an SPI interface, external parallel bus,
and digital audio interface.
The block diagram of the ADSP-21266
on Page 1
illustrates the
following architectural features:
Two processing elements, each containing an ALU, multi-
plier, shifter, and data register file
Data address generators (DAG1, DAG2)
Program sequencer with instruction cache
PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
Three programmable interval timers with PWM genera-
tion, PWM capture/pulse width measurement, and
external event counter capabilities
On-chip dual-ported SRAM (2M bit)
On-chip dual-ported, mask-programmable ROM
(4M bit)
JTAG test access port
8- or 16-bit parallel port that supports interfaces to off-chip
memory peripherals
DMA controller
Six full-duplex serial ports
SPI-compatible interface
Digital audio interface that includes two precision clock
generators (PCG), an input data port (IDP), six serial ports,
eight serial interfaces, a 20-bit synchronous parallel input
port, 10 interrupts, six flag outputs, six flag inputs, three
programmable timers, and a flexible signal routing unit
(SRU)
Figure 2
shows one sample configuration of a SPORT using the
precision clock generator to interface with an I
2
S ADC and an
I
2
S DAC with a much lower jitter clock than the serial port
would generate itself. Many other SRU configurations are
possible.
ADSP-21266 FAMILY CORE ARCHITECTURE
The ADSP-21266 is code compatible at the assembly level with
the ADSP-2136x and ADSP-2116x, and with the first generation
ADSP-2106x SHARC DSPs. The ADSP-21266 shares architec-
tural features with the ADSP-2136x and ADSP-2116x SIMD
SHARC family of DSPs, as detailed in the following sections.
SIMD Computational Engine
The ADSP-21266 contains two computational processing ele-
ments that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele-
ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive audio
algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Table 1. ADSP-21266 Benchmarks (at 200 MHz)
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with reversal) 61.3
μ
s
FIR Filter (per tap)
1
IIR Filter (per biquad)
1
Matrix Multiply (pipelined)
[3×3] × [3×1]
[4×4] × [4×1]
Divide (y/×)
Inverse Square Root
Speed
(at 200 MHz)
1
Assumes two files in multichannel SIMD mode.
3.3 ns
13.3 ns
30 ns
53.3 ns
20 ns
30 ns
相關(guān)PDF資料
PDF描述
ADSP-21266SKSTZ-1B SHARC Embedded Processor
ADSP-21266SKSTZ-1C SHARC Embedded Processor
ADSP-21266SKSTZ-2B SHARC Embedded Processor
ADSP-21266SKSTZ-2C SHARC Embedded Processor
ADSP-21266SKSTZ-2D SHARC Embedded Processor
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-21266SKSTZ-1B 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT 150MHZ 150MIPS 144LQFP - Trays
ADSP-21266SKSTZ-1C 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 150MHz 150MIPS 144-Pin LQFP 制造商:Analog Devices 功能描述:DSP FLOATING PT 32BIT 150MHZ 150MIPS 144LQFP - Trays
ADSP-21266SKSTZ-1D 功能描述:IC DSP 32BIT 150MHZ 144-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:SHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-21266SKSTZ-2B 制造商:Analog Devices 功能描述:DSP Floating-Point 32-Bit 200MHz 200MIPS 144-Pin LQFP
ADSP21266SKSTZ2C 制造商:Analog Devices 功能描述:
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