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參數(shù)資料
| 型號(hào)： | ADSP-21060CZ-160 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 240CQFP |
| 產(chǎn)品培訓(xùn)模塊： | SHARC Processor Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SHARC® |
| 類型： | 浮點(diǎn) |
| 接口： | 主機(jī)接口，連接端口，串行端口 |
| 時(shí)鐘速率： | 40MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 512kB |
| 電壓 - 輸入/輸出： | 5.00V |
| 電壓 - 核心： | 5.00V |
| 工作溫度： | -40°C ~ 100°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-CBFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-CQFP（32x32） |
| 包裝： | 托盤 |
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Rev. F
|
Page 12 of 64
|
March 2008
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
TFSx
I/O
Transmit Frame Sync (Serial Ports 0, 1).
RFSx
I/O
Receive Frame Sync (Serial Ports 0, 1).
LxDAT3–0
I/O
Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 k
: internal pull-down resistor that is enabled or
disabled by the LPDRD bit of the LCOM register.
LxCLK
I/O
Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 k
: internal pull-down resistor that is enabled or
disabled by the LPDRD bit of the LCOM register.
LxACK
I/O
Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 k
: internal pull-down resistor that is
enabled or disabled by the LPDRD bit of the LCOM register.
EBOOT
I
EPROM Boot Select. When EBOOT is high, the ADSP-2106x is configured for booting from an 8-bit EPROM.
When EBOOT is low, the LBOOT and BMS inputs determine booting mode. See the table in the BMS pin
description below. This signal is a system configuration selection that should be hardwired.
LBOOT
I
Link Boot. When LBOOT is high, the ADSP-2106x is configured for link port booting. When LBOOT is low,
the ADSP-2106x is configured for host processor booting or no booting. See the table in the BMS pin
description below. This signal is a system configuration selection that should be hardwired.
BMS
I/OT
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOT = 1, LBOOT = 0).
In a multiprocessor system, BMS is output by the bus master.
Input: When low, indicates that no booting will
occur and that ADSP-2106x will begin executing instructions from external memory. See table below. This
input is a system configuration selection that should be hardwired. *Three-statable only in EPROM boot
mode (when BMS is an output).
EBOOT
LBOOT
BMS
Booting Mode
1
0
Output
EPROM (Connect BMS to EPROM chip select.)
0
1 (Input)
Host Processor
0
1
1 (Input)
Link Port
0
0 (Input)
No Booting. Processor executes from external memory.
01
0 (Input)
Reserved
1
x (Input)
Reserved
CLKIN
I
Clock In. External clock input to the ADSP-2106x. The instruction cycle rate is equal to CLKIN. CLKIN should
not be halted, changed, or operated below the minimum specified frequency.
RESET
I/A
Processor Reset. Resets the ADSP-2106x to a known state and begins program execution at the program
memory location specified by the hardware reset vector address. This input must be asserted (low) at
power-up.
TCK
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
TMS
I/S
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k
: internal pull-up resistor.
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k
: internal pull-up
resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held
low for proper operation of the ADSP-2106x. TRST has a 20 k
: internal pull-up resistor.
EMU
O
Emulation Status. Must be connected to the ADSP-2106x EZ-ICE target board connector only.
ICSA
O
Reserved, leave unconnected.
VDD
P
Power Supply; nominally 5.0 V dc for 5 V devices or 3.3 V dc for 3.3 V devices. (30 pins).
GND
G
Power Supply Return. (30 pins).
NC
Do Not Connect. Reserved pins which must be left open and unconnected.
Table 3. Pin Descriptions (Continued)
Pin
Type
Function
A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain,
T = Three-State (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
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