參數(shù)資料
型號(hào)： ADSP-1981BL
廠商： Analog Devices, Inc.
元件分類： Codec
英文描述： AC 97 SoundMAX Codec
中文描述： 交流97 SoundMAX編解碼器
文件頁數(shù)： 26/32頁
文件大小： 326K
代理商： ADSP-1981BL
AD1981BL
EQ DATA REGISTER
Index 0x62
Rev. A | Page 26 of 32
Reg
No.
0x62
Name
EQ
Data
D15
CFD15
D14
CFD14
D13
CFD13
D12
CFD12
D11
CFD11
D10
CFD10
D9
CFD9
D8
CFD8
D7
CFD7
D6
CFD6
D5
CFD5
D4
CFD4
D3
CFD3
D2
CFD2
D1
CFD1
D0
CFD0
Default
0x0000
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the BCA
bits in the EQ Cntrl Register (0x60). Data is written to memory only if the EQM bit (Register 0x60, Bit 15) is asserted.
Table 37.
Bit
Mnemonic
Function
CFD [15:0]
Coefficient Data
The biquad coefficients are fixed-point format values with 16 bits of resolution. The CFD15 bit is
the MSB, and the CFD0 bit is the LSB.
MIXER ADC, INPUT GAIN REGISTER
Index 0x64
Reg
No.
0x64
Name
Mixer ADC,
Volume
D15
MXM
D14
X
D13
X
D12
X
D11
LMG3
D10
LMG2
D9
LMG1
D8
LMG0
D7
RM
1
D6
X
D5
X
D4
X
D3
RMG3
D2
RMG2
D1
RMG1
D0
RMG0
Default
0x8000
1
For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 39 for examples.
Table 38.
Bit
Mnemonic
Function
RMG [3:0]
Right Mixer Gain
Control
least significant bit represents 1.5 dB.
RM
Right-Channel Mute
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from
the MXM bit. Otherwise, this bit always reads 0 and has no affect when set to 1.
LMG [3:0]
Left Mixer Gain Control
This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB. The
least significant bit represents 1.5 dB.
MXM
Mixer Gain Register
Mute
1 = Muted (reset default).
This register controls the gain into the mixer ADC from 0 dB to a maximum gain of 22.5 dB. The
0 = Unmuted.
Table 39. Settings for Mixer ADC, Input Gain
Reg. 0x76
Control Bits Mixer ADC, Input Gain (0x64)
Left-Channel Mixer Gain D [11:8]
D15 Write
Readback
0
1111
1111
0
0000
0000
1
XXXX
XXXX
0
1111
1111
1
XXXX
XXXX
1
XXXX
XXXX
Right-Channel Mixer Gain D [3:0]
Readback
1111
0000
XXXX
XXXX
1111
XXXX
MSPLT
1
0
0
0
1
1
1
Function
22.5 dB Gain
0 dB Gain
∞ dB Gain, Muted
22.5 dB Gain
∞ dB Gain, Left Only Muted
∞ dB Gain, Left Muted
D7
1
X
X
X
1
0
1
Write
1111
0000
XXXX
XXXX
1111
XXXX
Function
22.5 dB Gain
0 dB Gain
∞ dB Gain, Muted
∞ dB Gain, Right Only Muted
22.5 dB Gain
∞ dB Gain, Right Muted
1
For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
X is a wild card, and has no effect on the value.
相關(guān)PDF資料
PDF描述
AD1981BL AC ’97 SoundMAX㈢ Codec
AD1981BLJSTZ2 AC ’97 SoundMAX㈢ Codec
AD1981BLJSTZ-REEL2 AC ’97 SoundMAX㈢ Codec
AD1981HD HD Audio SoundMAX Codec
AD1981HDJSTZ HD Audio SoundMAX Codec
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-2100 制造商:AD 制造商全稱:Analog Devices 功能描述:12.5 MIPS DSP Microprocessor
ADSP-2100A 制造商:AD 制造商全稱:Analog Devices 功能描述:ADSP-2100 Family DSP Microcomputers
ADSP-2100AJG 制造商:AD 制造商全稱:Analog Devices 功能描述:12.5 MIPS DSP Microprocessor
ADSP-2100AJP 制造商:AD 制造商全稱:Analog Devices 功能描述:12.5 MIPS DSP Microprocessor
ADSP-2100AKG 制造商:AD 制造商全稱:Analog Devices 功能描述:12.5 MIPS DSP Microprocessor
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*