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參數(shù)資料
| 型號： | ADS930E |
| 英文描述： | 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 8位，30MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 11/11頁 |
| 文件大?。?/td> | 191K |
| 代理商： | ADS930E |
11
ADS930
recommended to meet the rated performance specifications.
However, the ADS930 performance is tolerant to duty cycle
variations of as much as
±
10%, which should not affect the
performance. For applications operating with input frequen-
cies up to Nyquist (f
CLK
/2) or undersampling applications,
special considerations must be made to provide a clock with
very low jitter. Clock jitter leads to aperture jitter (t
A
) which
can be the ultimate limitation in achieving good SNR perfor-
mance. Equation (4) shows the relationship between aper-
ture jitter, input frequency and the signal-to-noise ratio:
SNR = 20log10 [1/(2
π
f
IN
t
A
)]
(4)
recommended to limit the fan-out to one in order to keep the
capacitive loading on the data lines below the specified
15pF. If necessary, external buffers or latches may be used
to provide the added benefit of isolating the A/D converter
from any digital activities on the bus coupling back high
frequency noise which degrades the performance.
POWER-DOWN MODE
The ADS930’s low power consumption can be reduced even
further by initiating a power-down mode. For this, the Power
Down Pin (Pin 17) must be tied to a logic “High” reducing
the current drawn from the supply by approximately 70%. In
normal operation, the power-down mode is disabled by an
internal pull-down resistor (50k
).
During power-down, the digital outputs are set in 3-state.
With the clock applied, the converter does not accurately
process the sampled signal. After removing the power-down
condition, the output data from the following 5 clock cycles
is invalid (data latency).
DECOUPLING AND GROUNDING
CONSIDERATIONS
The ADS930 has several supply pins, one of which is
dedicated to supply only the output driver (LV
DD
). The
remaining supply pins are not divided into analog and digital
supply pins since they are internally connected on the chip.
For this reason, it is recommended that the converter be
treated as an analog component and to power it from the
analog supply only. Digital supply lines often carry high
levels of noise which can couple back into the converter and
limit performance.
Because of the pipeline architecture, the converter also
generates high frequency transients and noise that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed.
Figure 8 shows the recommended decoupling scheme for the
analog supplies. In most cases 0.1
μ
F ceramic chip capacitors
are adequate to keep the impedance low over a wide fre-
quency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore, they
should be located as close as possible to the supply pins.
DIGITAL OUTPUTS
There is a 5.0 clock cycle data latency from the start convert
signal to the valid output data. The standard output coding
is Straight Offset Binary where a full scale input signal
corresponds to all “1’s” at the output. The digital outputs of
the ADS930 can be set to a high impedance state by driving
the OE (pin 16) with a logic “HI”. Normal operation is
achieved with pin 16 “LO” or Floating due to internal pull-
down resistors. This function is provided for testability
purposes but is not recommended to be used dynamically.
The digital outputs of the ADS930 are standard CMOS
stages and designed to be compatible to both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: V
OL
= 0.4V, V
OH
= 2.4V, which allows
the ADS930 to directly interface to 3V-logic. The digital
output driver of the ADS930 uses a dedicated digital supply
pin (pin 2, LV
DD
) see Figure 7. By adjusting the voltage on
LV
DD
, the digital output levels will vary respectively. It is
TABLE I. Coding Table for the ADS930.
+FS (IN = +2V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +1.5V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +1V)
11111111
11111111
11111110
11100000
11000000
10100000
10000001
10000000
01111111
01100000
01000000
00100000
00000001
00000000
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
SINGLE-ENDED INPUT
(IN = 1.5V DC)
+V
S
+LV
DD
ADS930
Digital
Output
Stage
FIGURE 7. Independent Supply Connection for Output
Stage.
V
S
1
13
14
GND
ADS930
0.1μF
V
S
18
19
20
GND
0.1μF
V
S
28
0.1μF
FIGURE 8. Recommended Bypassing for Analog Supply
Pins.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS930E | 制造商:Texas Instruments 功能描述:IC's |
| ADS930E/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 30 MSPS SE/ Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS930E/1KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 30 MSPS SE/ Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS930EG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Bit 30 MSPS SE/ Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS-930MC | 制造商:Murata Power Solutions 功能描述:Single ADC Pipelined 500ksps 16-bit Parallel 40-Pin TDIP |
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