- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375266 > ADS901E 10-Bit, 20MHz, #V Supply ANALOG-TO-DIGITAL CONVERTER PDF資料下載
參數(shù)資料
| 型號(hào)： | ADS901E |
| 英文描述： | 10-Bit, 20MHz, #V Supply ANALOG-TO-DIGITAL CONVERTER |
| 文件頁(yè)數(shù)： | 11/11頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | ADS901E |
11
ADS901
DIGITAL OUTPUTS
There is a 5.0 clock cycle data latency from the start convert
signal to the valid output data. The standard output coding
is Straight Offset Binary where a full scale input signal
corresponds to all “1’s” at the output. The digital outputs of
the ADS901 can be set to a high impedance state by driving
the three-state (pin 16) with a logic “HI”. Normal operation
is achieved with pin 16 “LO” or Floating due to internal
pull-down resistors. This function is provided for testability
purposes but is not recommended to be used dynamically.
The digital outputs of the ADS901 are standard CMOS
stages and designed to be compatible to both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: V
OL
= 0.4V, V
OH
= 2.4V, which allows
the ADS901 to directly interface to 3V-logic. The digital
outputs of the ADS901 use a dedicated digital supply pin
(pin 2, LV
DD
). By adjusting the voltage on LV
DD
, the digital
output levels will vary respectively. In any case, it is recom-
mended to limit the fan-out to one, to keep the capacitive
loading on the data lines below the specified 15pF. If
necessary, external buffers or latches may be used to provide
the added benefit of isolating the A/D converter from any
digital activities on the bus coupling back high frequency
noise and degrading the performance.
POWER-DOWN MODE
The ADS901’s low power consumption can be further
reduced by initiating a power down mode. For this, the
Pwrdn-Pin (Pin 17) must be tied to a logic “High” reducing
the current drawn from the supply by approximately 70%. In
normal operation the power-down mode is disabled by an
internal pull-down resistor (50k
).
FIGURE 6. Precise Solution to Supply External Reference
Voltages.
+V
S
+LV
DD
ADS901
Digital
Output
Stage
FIGURE 7. Independent Supply Connection for Output
Stage.
During power-down the digital outputs are set in 3-state.
With the clock applied, the converter does not accurately
process the sampled signal. After removing the power-down
condition the output data from the following 5 clock cycles
is invalid (data latency).
DECOUPLING AND GROUNDING
CONSIDERATIONS
The ADS901 converter have several supply pins, one of
which is dedicated to supply only the output driver. The
remaining supply pins are not, as is often the case, divided
into analog and digital supply pins since they are internally
connected on the chip. For this reason it is recommended to
treat the converter as an analog component and to power it
from the analog supply only. Digital supply lines often carry
high levels of noise which can couple back into the converter
and limit the achievable performance.
Because of the pipeline architecture, the converter also
generates high frequency transients and noise that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed.
Figure 8 shows the recommended decoupling scheme for the
analog supplies. In most cases 0.1
μ
F ceramic chip capacitors
are adequate to keep the impedance low over a wide fre-
quency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore they should
be located as close to the supply pins as possible.
FIGURE 8. Recommended Bypassing for Analog Supply
Pins.
+V
S
1
13
14
GND
ADS901
0.1μF
+V
S
18
19
20
GND
0.1μF
+V
S
28
0.1μF
1/2 A
1
R
F1
R
G1
3k
5k
REF1004
+1.2V
10k
10
Top
Reference
(REFT)
+V
S
+V
S
1/2 A
1
R
F2
R
G2
10
Bottom
Reference
(REFB)
A
1
= OPA2237 or Equivalent.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS902 | 10-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS902E | 10-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS930 | 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS930E | 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS931 | 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS901E | 制造商:Texas Instruments 功能描述:Analog-Digital Converter IC Number of Bi |
| ADS901E/1K | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10-Bit 20 MSPS SE/Diff Input RoHS:否 制造商:Texas Instruments 輸入信號(hào)類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| ADS901E/1KG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10-Bit 20 MSPS SE/Diff Input RoHS:否 制造商:Texas Instruments 輸入信號(hào)類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| ADS901EG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 20 MSPS SE/Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS902 | 制造商:BB 制造商全稱:BB 功能描述:10-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。