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參數(shù)資料
| 型號： | ADS901 |
| 英文描述： | 10-Bit, 20MHz, #V Supply ANALOG-TO-DIGITAL CONVERTER |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 174K |
| 代理商： | ADS901 |
8
ADS901
402
A1
V
IN
402
R
1
1k
V
CM
C
1
0.1
μ
F
0.1
μ
F
IN
CM
+5V
R
1
50
–5V
+3V
ADS901
THEORY OF OPERATION
The ADS901 is a high speed sampling analog-to-digital
converter that utilizes a pipeline architecture. The fully
differential topology and digital error correction guarantee
10-bit resolution. The differential track/hold circuit is shown
in Figure 1. The switches are controlled by an internal clock
which has a non-overlapping two phase signal,
φ
1 and
φ
2. At
the sampling time the input signal is sampled on the bottom
plates of the input capacitors. In the next clock phase,
φ
1, the
bottom plates of the input capacitors are connected together
and the feedback capacitors are switched to the op amp
output. At this time the charge redistributes between C
I
and
C
H
, completing one track/hold cycle. The differential output
is a held DC representation of the analog input at the sample
time. The track/hold circuit can also convert a single-ended
input signal into a fully differential signal for the quantizer.
Consequently, the input signal-to-noise performance. Other
parameters such as small-signal and full-power bandwidth,
and wideband noise are also defined in this stage.
To accommodate a bipolar signal swing, the ADS901 oper-
ates with a common-mode voltage (V
CM
) which is derived
from the external references. Due to the symmetric resistor
ladder inside the ADS901, the V
CM
is situated between the
top and bottom reference voltage. Equation (1) can be used
for calculating the common-mode voltage level.
V
CM
= (REFT +REFB)/2
(1)
There is a 5.0 clock cycle data latency from the start convert
signal to the valid output data. The standard output coding
is Straight Offset Binary where a full scale input signal
corresponds to all “1’s” at the output. The digital outputs of
the ADS901 can be set to a high impedance state by driving
the three-state (pin 16) with a logic “HI”. Normal operation
is achieved with pin 16 “LO” or Floating due to internal
pull-down resistors. This function is provided for testability
purposes but is not recommended to be used dynamically.
APPLICATIONS
SIGNAL SWING AND COMMON-MODE
CONSIDERATIONS
The ADS901 is designed to operate on a +3V single supply
voltage. The nominal input signal swing is 1Vp-p, situated
between +1V and +2V. This means that the signal swings
±
0.5V around a common-mode voltage of +1.5V, which is
half the supply voltage (V
CM
= V
S
/2). In some applications
it might be advantageous to increase the input signal swing.
This will improve the achievable signal-to-noise perfor-
mance. However, considerations should be made to keep the
signal swing within the linear range of operation of the
driving circuitry to avoid any excessive distortion. In ex-
treme situations the performance of the converter will start
to degrade due to variations of the input’s switch on-
resistance over the input voltage. Therefore, the signal swing
should remain approximately 0.5V away from each rail
during normal operation.
DRIVING THE ANALOG INPUTS
AC-COUPLED DRIVER
Figure 2 shows an example of an ac-coupled, single-ended
interface circuit using a high-speed op amp that operates on
φ
1
φ
1
φ
2
φ
1
φ
1
φ
1
φ
1
φ
1
φ
2
φ
1
φ
2
φ
1
φ
2
IN
IN
OUT
OUT
Op Amp
Bias
V
CM
Op Amp
Bias
V
CM
C
H
C
I
C
I
C
H
Input Clock (50%)
Internal Non-overlapping Clock
FIGURE 1. Input Track/Hold Configuration with Timing
Signals.
The pipelined quantizer architecture has 9 stages with each
stage containing a two-bit quantizer and a two bit digital-
to-analog converter, as shown in Figure 2. Each two-bit
quantizer stage converts on the edge of the sub-clock, which
is the same frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to
time-align it with the data created from the following quan-
tizer stages. This aligned data is fed into a digital error
correction circuit which can adjust the output data based on
the information found on the redundant bits. This technique
provides the ADS901 with excellent differential linearity
and guarantees no missing codes at the 10-bit level.
FIGURE 2. AC-Coupled, Single-Ended Interface Circuit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS901E | 10-Bit, 20MHz, #V Supply ANALOG-TO-DIGITAL CONVERTER |
| ADS902 | 10-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS902E | 10-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS930 | 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS930E | 8-Bit, 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS901E | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 20 MSPS SE/Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS901E | 制造商:Texas Instruments 功能描述:Analog-Digital Converter IC Number of Bi |
| ADS901E/1K | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10-Bit 20 MSPS SE/Diff Input RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| ADS901E/1KG4 | 功能描述:視頻模擬/數(shù)字化轉(zhuǎn)換器集成電路 10-Bit 20 MSPS SE/Diff Input RoHS:否 制造商:Texas Instruments 輸入信號類型:Differential 轉(zhuǎn)換器數(shù)量:1 ADC 輸入端數(shù)量:4 轉(zhuǎn)換速率:3 Gbps 分辨率:8 bit 結(jié)構(gòu): 輸入電壓:3.3 V 接口類型:SPI 信噪比: 電壓參考: 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TCSP-48 封裝:Reel |
| ADS901EG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 10-Bit 20 MSPS SE/Diff Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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