參數(shù)資料
型號(hào): ADS8506IBDW
英文描述: 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
中文描述: 12位40 kSPS的低功耗采樣模擬到數(shù)字轉(zhuǎn)換的內(nèi)部基準(zhǔn),并行/串行接口
文件頁數(shù): 12/28頁
文件大?。?/td> 426K
代理商: ADS8506IBDW
www.ti.com
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16
15
ADS8506
+5 V
+
+
Convert Pulse
40 ns Min
200
0.1
μ
F
10
μ
F
100
+
2.2
μ
F
66.5 k
Serial Output
NC
(1)
BUSY
R/C
SDATA
±
10 V
+ 5 V
22
μ
F
+
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
DATACLK
STARTING A CONVERSION
The combination of CS (pin 23) and R/C (pin 22) low for a minimum of 40 ns puts the sample-and-hold of the
ADS8506 in the hold state and starts conversion
N
. BUSY (pin 24) goes low and stays low until conversion
N
is
completed and the internal output register has been updated. All new convert commands during BUSY low are
ignored. CS and/or R/C must go high before BUSY goes high, or a new conversion is initiated without sufficient
time to acquire a new signal.
ADS8506
SLAS484A–SEPTEMBER 2007–REVISED OCTOBER 2007
Figure 32. Basic ±10-V Operation With Serial Output
The ADS8506 begins tracking the input signal at the end of the conversion. Allowing 25
μ
s between convert
commands assures accurate acquisition of a new signal. Refer to
Table 2
and
Table 3
for a summary of CS,
R/C, and BUSY states, and
Figure 33
,
Figure 34
,
Figure 35
,
Figure 36
,
Figure 37
,
Figure 38
, and
Figure 39
for
timing diagrams.
Table 2. Control Functions When Using Parallel Output (DATACLK Tied Low, EXT/INT Tied High)
CS
1
R/C
X
0
BUSY
X
1
1
OPERATION
None. Data bus is in Hi-Z state.
Initiates conversion
N
. Data bus remains in Hi-Z state.
Initiates conversion
N
. Databus enters Hi-Z state.
Conversion
N
completed. Valid data from conversion
N
on the databus.
Enables databus with valid data from conversion
N
.
Enables databus with valid data from conversion
N–1
(1)
. Conversion
N
in progress.
Enables databus with valid data from conversion
N–1
(1)
. Conversion
N
in progress.
New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C
must be HIGH when BUSY goes HIGH.
New convert commands ignored. Conversion
N
in progress.
0
0
1
1
1
1
0
0
0
0
0
X
X
0
(1)
See
Figure 33
and
Figure 34
for constraints on data valid from conversion N–1.
CS and R/C are internally ORed and level triggered. It is not a requirement which input goes low first when
initiating a conversion. If, however, it is critical that CS or R/C initiates conversion
N
, be sure the less critical
input is low at least t
su2
10 ns prior to the initiating input. If EXT/INT (pin 8) is low when initiating conversion
N
,
serial data from conversion
N–1
is output on SDATA (pin 19) following the start of conversion
N
. See Internal
Data Clock in the Reading Data section.
12
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Copyright 2007, Texas Instruments Incorporated
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ADS8506
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ADS8506IBDWR 12-BIT 40-KSPS LOW POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH INTERNAL REFERENCE AND PARALLEL/SERIAL INTERFACE
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ADS8506IBDWRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B 80KSPS Lo Pwr Int Ref ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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