參數(shù)資料
型號： ADS8504IBDWRG4
英文描述： 12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
中文描述： 12位250 kSPS的采樣CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù)： 13/19頁
文件大?。?/td> 361K
代理商： ADS8504IBDWRG4
www.ti.com
APPLICATION INFORMATION
CALIBRATION
The ADS8504 can be trimmed in hardware or software. The offset should be trimmed before the gain since the
offset directly affects the gain. To achieve optimum performance, several iterations may be required.
Hardware Calibration
To calibrate the offset and gain of the ADS8504, install the proper resistors and potentiometers as shown in
Figure 23
(a).
Software Calibration
To calibrate the offset and gain of the ADS8504 in software, no external resistors are required. See the No
Calibration section for details on the effects of the external resistors. Refer to
Table 4
for range of offset and gain
errors with and without external resistors.
No Calibration
See
Figure 23
(b) for circuit connections. The external resistors shown in
Figure 23
(b) may not be necessary in
some applications. These resistors provide compensation for an internal adjustment of the offset and gain which
allows calibration with a single supply. Refer to
Table 4
for range of offset and gain errors with and without
external resistors.
1
2
3
4
5
AGND2
CAP
REF
AGND1
VIN
+
+5 V
+
Gain
Offset
1
2
3
4
5
AGND2
CAP
REF
AGND1
VIN
+
+
±
10 V
200
33.2 k
50 k
50 k
2.2
μ
F
2.2
μ
F
2.2
μ
F
2.2
μ
F
200
33.2 k
±
10 V
(a)
±
10 V With Hardware Trim
(b)
±
10 V Without Hardware Trim
Note: Use 1% metal film resistors.
576 k
REFERENCE
The ADS8504 can operate with its internal 2.5-V reference or an external reference. By applying an external
reference to pin 5, the internal reference can be bypassed. The reference voltage at REF is buffered internally
with the output on CAP (pin 4).
ADS8504
SLAS434–JUNE 2005
Table 4. Typical Offset (Bipolar Zero Error, BPZ) and Gain Errors With and Without External Resistors
WITH EXTERNAL RESISTORS
-4.88 < BPZ < 4.88
-1 < BPZ < 1
-0.25 < Error < 0.25
-0.25 < Error < 0.25
WITHOUT EXTERNAL RESISTORS
-56.6 < BPZ < -32.2
-11.6 < BPZ < -6.6
-2.5 < Error < -1.25
-3.5 < Error < -2.25
UNITS
mV
LSBs
BPZ
+Full scale
–Full scale
Gain error
% of FSR
Figure 23. Circuit Diagram With and Without External Trim Hardware
The internal reference has an 8 ppm/°C drift (typical) and accounts for approximately 20% of the full-scale error
(FSE = ±0.5%).
13
相關(guān)PDF資料
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