參數(shù)資料
型號(hào): ADS8504IBDW
英文描述: 12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
中文描述: 12位250 kSPS的采樣CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 8/19頁
文件大?。?/td> 361K
代理商: ADS8504IBDW
www.ti.com
160
140
120
100
80
60
40
20
0
20
0
25
50
75
100
125
A
f Frequency Hz
Figure 15.
8192 Points
f
s
= 250 KSPS
f
= 1 kHz, 0dB
SINAD = 73.47 dB
THD = 94.03 dB
A
f Frequency Hz
Figure 16.
160
140
120
100
80
60
40
20
0
20
0
25
50
75
100
125
8192 Points
f
s
= 250 KSPS
f
= 45 kHz, 0dB
SINAD = 73.62 dB
THD = 94.03 dB
BASIC OPERATION
STARTING A CONVERSION
ADS8504
SLAS434–JUNE 2005
Typical Characteristics (continued)
FFT
FFT
Figure 17
shows a basic circuit to operate the ADS8504 with a full parallel data output. Taking R/C (pin 24) low
for a minimum of 40 ns (1.75 μs max if BUSY is used to latch the data) initiates a conversion. BUSY (pin 26)
goes low and stays low until the conversion is completed and the output registers are updated. Data is output in
binary 2's complement with the MSB on pin 6. BUSY going high can be used to latch the data. All convert
commands are ignored while BUSY is low.
The ADS8504 begins tracking the input signal at the end of the conversion. Allowing 4 μs between convert
commands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external trimming with a single supply. The external resistors
compensate for this adjustment and can be left out if the offset and gain are corrected in software (refer to the
Calibration section).
The combination of CS (pin 25) and R/C (pin 24) low for a minimum of 40 ns immediately puts the sample/hold of
the ADS8504 in the hold state and starts conversion
n
. BUSY (pin 26) goes low and stays low until conversion
n
is completed and the internal output register has been updated. All new convert commands during BUSY low are
ignored. CS and/or R/C must go high before BUSY goes high or a new conversion is initiated without sufficient
time to acquire a new signal.
The ADS8504 begins tracking the input signal at the end of the conversion. Allowing 4 μs between convert
commands assures accurate acquisition of a new signal. Refer to
Table 1
for a summary of CS, R/C, and BUSY
states and
Figure 19
,
Figure 20
, and
Figure 21
for the timing diagrams.
8
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ADS8505 制造商:TI 制造商全稱:Texas Instruments 功能描述:16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
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