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參數(shù)資料
| 型號： | ADS8504IB |
| 英文描述： | 12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 12位250 kSPS的采樣CMOS模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 361K |
| 代理商： | ADS8504IB |
www.ti.com
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28
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25
24
23
22
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16
15
ADS8504
+5V
+
+
+
+
Convert Pulse
40 ns Min
200
2.2
μ
F
0.1
μ
F
10
μ
F
33.2 k
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
DZ Low
DZ Low
DZ Low
DZ Low
D0 (LSB)
D1
D2
D3
2.2
μ
F
BUSY
R/C
READING DATA
The ADS8504 outputs full or byte-reading parallel data in binary 2's complement data output format. The parallel
output is active when R/C (pin 24) is high and CS (pin 25) is low. Any other combination of CS and R/C 3-states
the parallel output. Valid conversion data can be read in a full parallel, 12-bit word or two 8-bit bytes on pins 6-13
and pins 15-22. BYTE (pin 23) can be toggled to read both bytes within one conversion cycle. Refer to
Table 2
for ideal output codes and
Figure 18
for bit locations relative to the state of BYTE.
ADS8504
SLAS434–JUNE 2005
BASIC OPERATION (continued)
CS and R/C are internally ORed and level triggered. There is not a requirement which input goes low first when
initiating a conversion. If, however, it is critical that CS or R/C initiates conversion
n
, be sure the less critical input
is low at least 10 ns prior to the initiating input.
To reduce the number of control pins, CS can be tied low using R/C to control the read and convert modes. The
parallel output becomes active whenever R/C goes high. Refer to the READING DATA section.
Table 1. Control Line Functions for Read and Convert
CS
1
↓
0
0
↓
↓
0
0
R/C
X
0
↓
1
1
1
↑
0
BUSY
X
1
1
↑
1
0
0
↑
OPERATION
None. Databus is in Hi-Z state.
Initiates conversion
n
. Databus remains in Hi-Z state.
Initiates conversion
n
. Databus enters Hi-Z state.
Conversion
n
completed. Valid data from conversion
n
on the databus.
Enables databus with valid data from conversion
n
.
Enables databus with valid data from conversion
n-1
(1)
. Conversion
n
in progress.
Enables databus with valid data from conversion
n-1
(1)
. Conversion
n
in progress.
New conversion initiated without acquisition of a new signal. Data is invalid. CS and/or R/C
must be high when BUSY goes high.
New convert commands ignored. Conversion
n
in progress.
X
X
0
(1)
See
Figure 19
and
Figure 20
for constraints on data valid from conversion
n-1
.
Figure 17. Basic Operation
9
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8504IBDW | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 250kHz CMOS w/Parallel Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8504IBDWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 250kHz CMOS w/Parallel Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8504IBDWR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 250kHz CMOS w/Parallel Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8504IBDWRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 250kHz CMOS w/Parallel Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8505 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:16-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER |
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