參數(shù)資料
型號: ADS8504
英文描述: 12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
中文描述: 12位250 kSPS的采樣CMOS模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 10/19頁
文件大小: 361K
代理商: ADS8504
www.ti.com
PARALLEL OUTPUT (After a Conversion)
After conversion
n
is completed and the output registers have been updated, BUSY (pin 26) goes high. Valid
data from conversion
n
is available on D11-D0 (pins 6-13 and 15-18). BUSY going high can be used to latch the
data. Refer to
Table 3
and
Figure 19
,
Figure 20
, and
Figure 21
for timing specifications.
PARALLEL OUTPUT (During a Conversion)
After conversion
n
has been initiated, valid data from conversion
n-1
can be read and is valid up to t
(2.2 μs typ)
after the start of conversion
n
. Do not attempt to read data from t
2
(2.2 μs typ) after the start of conversion
n
until
BUSY (pin 26) goes high; this may result in reading invalid data. Refer to
Table 3
and
Figure 19
,
Figure 20
, and
Figure 21
for timing specifications.
ADS8504
SLAS434–JUNE 2005
Table 2. Ideal Input Voltages and Output Codes
DIGITAL OUTPUT BINARY 2's COMPLEMENT
BINARY CODE
DESCRIPTION
ANALOG INPUT
HEX CODE
Full-scale range
Least significant bit (LSB)
Full scale (10 V-1 LSB)
Midscale
One LSB below midscale
-Full scale
±10 V
4.88 mV
9.99512 V
0 V
-4.88 mV
-10 V
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
7FF
000
FFF
800
Note:
For the best possible performance, data should not be read during a conversion. The switching noise of
the asynchronous data transfer can cause digital feedthrough degrading the converter's performance.
The number of control lines can be reduced by tying CS low while using the falling edge of R/C to initiate
conversions and the rising edge of R/C to activate the output mode of the converter. See
Figure 19
.
Table 3. Conversion Timing
SYMBOL
t
w1
t
a
t
pd
t
w2
t
d1
t
d2
t
conv
t
acq
t
dis
t
d3
t
v
t
conv
+ t
acq
t
su
t
c
t
en
t
d4
DESCRIPTION
Pulse duration, convert
Access time, data valid after R/C low
Propagation delay time, BUSY from R/C low
Pulse duration, BUSY low
Delay time, BUSY after end of conversion
Delay time, aperture
Conversion time
Acquisition time
Disable time, bus
Delay time, BUSY after data valid
Valid time, previous data remains valid after R/C low
Throughput time
Setup time, R/C to CS
Cycle time between conversions
Enable time, bus
Delay time, BYTE
MIN
40
TYP
MAX
1750
3.2
25
2.2
UNITS
ns
μs
ns
μs
ns
ns
μs
μs
ns
ns
μs
μs
ns
μs
ns
ns
2.2
15
5
5
2.2
1.8
10
35
1.5
30
50
2
83
4
10
4
10
5
30
10
83
30
10
相關(guān)PDF資料
PDF描述
ADS8504IB 12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
ADS8504IBDW 12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS8504IB 制造商:BB 制造商全稱:BB 功能描述:12-BIT 250-KSPS SAMPLING CMOS ANALOG-TO-DIGITAL CONVERTER
ADS8504IBDW 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 250kHz CMOS w/Parallel Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8504IBDWG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 250kHz CMOS w/Parallel Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8504IBDWR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 250kHz CMOS w/Parallel Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS8504IBDWRG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 250kHz CMOS w/Parallel Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32