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參數(shù)資料
| 型號： | ADS8482IBRGZR |
| 英文描述： | 18-BIT, 1-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE |
| 中文描述： | 18位，1 MSPS的，偽雙極，全差分輸入，微采樣模擬到數(shù)字轉(zhuǎn)換并行接口，參考 |
| 文件頁數(shù)： | 24/31頁 |
| 文件大?。?/td> | 647K |
| 代理商： | ADS8482IBRGZR |
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Reading Data
ADS8482
SLAS386A–JULY 2005–REVISED JUNE 2006
PRINCIPLES OF OPERATION (continued)
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8482 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high immediately
following CONVST going low. BUSY stays high throughout the conversion process and returns low when the
conversion has ended.
Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS
when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
The ADS8482 outputs full parallel data in straight binary format as shown in
Table 1
. The parallel output is
active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of
CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read
should attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE
and BUS18/16 are used for multiword read operations. BYTE is used whenever lower bits on the bus are output
on the higher byte of the bus. BUS18/16 is used whenever the last two bits on the 18-bit bus is output on either
bytes of the higher 16-bit bus. Refer to
Table 1
for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
Full scale range
Least significant bit (LSB)
+Full scale
Midscale
Midscale – 1 LSB
Zero
ANALOG VALUE
+V
ref
2
×
(+V
ref
)/262144
(+V
ref
) – 1 LSB
0 V
0 V – 1 LSB
–V
ref
DIGITAL OUTPUT STRAIGHT BINARY
BINARY CODE
01 1111 1111 1111 1111
00 0000 0000 0000 0000
11 1111 1111 1111 1111
10 0000 0000 0000 0000
HEX CODE
1FFFF
00000
3FFFF
20000
The output data is a full 18-bit word (D17–D0) on DB17–DB0 pins (MSB–LSB) if both BUS18/16 and BYTE are
low.
The result may also be read on an 16-bit bus by using only pins DB17–DB2. In this case two reads are
necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 16 most significant bits
(D17–D2) on pins DB17–DB2, then bringing BUS18/16 high while holding BYTE low. When BUS18/16 is high,
the lower two bits (D1–D0) appear on pins DB3–DB2.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB17–DB10. In
this case three reads are necessary: the first as before, leaving both BUS18/16 and BYTE low and reading the 8
most significant bits on pins DB17–DB10, then bringing BYTE high while holding BUS18/16 low. When BYTE is
high, the medium bits (D9–D2) appear on pins DB17–DB10. The last read is done by bringing BUS18/16 high
while holding BYTE high. When BUS18/16 is high, the lower two bits (D1–D0) appear on pins DB11–DB10. The
last read cycle is not necessary if only the first 16 most significant bits are of interest.
All of these multiword read operations can be performed with multiple active RD (toggling) or with RD held low
for simplicity. This is referred to as the AUTO READ operation.
Table 2. Conversion Data Read Out
DATA READ OUT
PINS
DB9–DB4
All One's
All One's
BYTE
BUS18/16
PINS
PINS
PINS
DB3–DB2
All One's
D1–D0
PINS
DB1–DB0
All One's
All One's
DB17–DB12
All One's
All One's
DB11–DB10
D1–D0
All One's
High
Low
High
High
24
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參數(shù)描述 |
|---|---|
| ADS8482IBRGZRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 1MSPS Parall ADC w/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8482IBRGZT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 1MSPS Parall ADC w/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8482IBRGZTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 1MSPS Parall ADC w/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8482IRGZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 1MSPS Parall ADC w/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8482IRGZRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 1MSPS Parall ADC w/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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