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參數(shù)資料
| 型號： | ADS8481IBPFBT |
| 英文描述： | 18-BIT, 1-MSPS, PSEUDO-DIFFERENTIAL UNIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE |
| 中文描述： | 18位，1 MSPS的，偽差分單極輸入，微采樣模擬到數(shù)字轉(zhuǎn)換并行接口和參考 |
| 文件頁數(shù)： | 22/31頁 |
| 文件大?。?/td> | 717K |
| 代理商： | ADS8481IBPFBT |
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ADS8481
_
+
20
W
680 pF
Low-Pass Filter
THS4031
V
IN
380
W
INP
INM
380
W
Bipolar to Unipolar Conversion
Vdc
DIGITAL INTERFACE
Timing and Control
Reading Data
ADS8481
SLAS385A–FEBRUARY 2006–REVISED MARCH 2006
PRINCIPLES OF OPERATION (continued)
Figure 41. Input Circuit
See the timing diagrams in the specifications section for detailed information on timing signals and their
requirements.
The ADS8481 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8481 switches from
the sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of
this signal is important to the performance of the converter. The BUSY output is brought high immediately
following CONVST going low. BUSY stays high throughout the conversion process and returns low when the
conversion has ended.
Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS
when BUSY is low.
Both RD and CS can be high during and before a conversion with one exception (CS must be low when
CONVST goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the
parallel output bus with the conversion.
The ADS8481 outputs full parallel data in straight binary format as shown in
Table 1
. The parallel output is
active when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of
CONVST. This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read
should attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE
and BUS18/16 are used for multiword read operations. BYTE is used whenever lower bits on the bus are output
on the higher byte of the bus. BUS18/16 is used whenever the last two bits on the 18-bit bus is output on either
bytes of the higher 16-bit bus. Refer to
Table 1
for ideal output codes.
22
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參數(shù)描述 |
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| ADS8481IBRGZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 1MSPS Parall ADC w/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8481IBRGZRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 1MSPS Parall ADC w/Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8481IBRGZT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 1-MSPS Pseudo Diff Unipolar Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8481IBRGZTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 1-MSPS Pseudo Diff Unipolar Input RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8481IPFBR | 制造商:BB 制造商全稱:BB 功能描述:18-BIT, 1-MSPS, PSEUDO-DIFFERENTIAL UNIPOLAR INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE |
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