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參數(shù)資料
| 型號： | ADS8422IPFBT |
| 英文描述： | 16-BIT, 4-MSPS, PSEUDO-BIPOLAR, FULLY DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE, REFERENCE |
| 中文描述： | 16位4 MSPS的，偽雙極，全差分輸入，微采樣模擬到數(shù)字轉(zhuǎn)換并行接口，參考 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 816K |
| 代理商： | ADS8422IPFBT |
www.ti.com
TIMING CHARACTERISTICS FROM DIGITAL INPUTS
All specifications typical at –40
°
C to 85
°
C, +VBD = 2.7 V to 5.25 V
(1)(2)
TIMING CHARACTERISTICS OF DIGITAL OUTPUTS
All specifications typical at –40
°
C to 85
°
C, +VBD = 2.7 V to 5.25 V
(1)(2)
ADS8422
SLAS512B–JUNE 2006–REVISED DECEMBER 2006
PARAMETER
MIN
TYP
MAX
UNIT
CONVERSION AND ACQUISITION
t
(ACQ)
Acquisition time, internal to device, not externally visible
t
w1
Pulse duration, CONVST low
t
w2
Pulse duration, CONVST high
t
p1
Period, CONVST
t
q1
Quiet time, last toggle of interface input signals during acquisition before CONVST falling
(3)
t
q2
Quiet time, CONVST falling to first toggle of interface input signals
(3)
POWER DOWN
PD1 low for only ADC reset (no powerdown)
t
w3
Pulse duration
PD1 low for ADC reset and also ADC powerdown
PD2 low pulse duration for REFOUT and COMMOUT buffers powerdown
Pulse duration, all others unspecified
70
20
ns
ns
ns
ns
ns
ns
100
250
30
10
20
500
1500
1500
ns
10
ns
(1)
(2)
All input signals are specified with t
= t
= 5 ns (10% to 90% of V
) and timed from after 90% of transition.
All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching
90% of transition.
Quiet time zones are for meeting performance and not functionality.
(3)
PARAMETER
MIN
TYP
MAX
UNIT
CONVERSION AND ACQUISITION
t
(CONV)
Conversion time, internal to device, not externally visible
t
d1
Delay time, CONVST fall to conversion start (aperture delay)
DATA READ OPERATION
t
d2
Delay time, CONVST low to data valid if CS = RD = 0
t
d3
Delay time, data valid to BUSY low if CS = RD = 0
t
d4
Delay time, RD (or CS) low to data valid
t
d5
Delay time, BYTE toggle to data valid
t
d6
Delay time, data three-state after RD (or CS) high
POWER DOWN
t
d7
Delay time, PD1 low to BUSY rising
Delay time, PD1 high to device operational (with PD2 held high)
t
d8
Delay time, PD2 high to REFOUT/COMMOUT valid
Delay time, power up (after AV
DD
= 4.75 V)
t
d9
Delay time, data three-state after PD1 low
180
ns
ns
3
225
ns
ns
ns
ns
ns
5
17
20
12
20
5
25
25
1.5
ns
μ
s
ms
ms
μ
s
(1)
(2)
All input signals are specified with t
= t
= 5 ns (10% to 90% of V
) and timed from after 90% of transition.
All digital output signals loaded with 10-pF capacitors at +VBD = 2.7 V and 20-pF capacitor at +VBD = 5.25 V and timed to reaching
90% of transition.
6
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