參數(shù)資料
型號： ADS8413IRGZR
英文描述： 16-BIT, 2-MSPS, LVDS SERIAL INTERFACE, SAR ANALOG-TO-DIGITAL CONVERTER
中文描述： 16位，2 MSPS的LVDS串行接口，SAR類比數(shù)位轉(zhuǎn)換器
文件頁數(shù)： 9/38頁
文件大?。?/td> 1197K
代理商： ADS8413IRGZR
www.ti.com
DETAILED DESCRIPTION
SAMPLE AND CONVERT
The sampling and conversion process is controlled by the CSTART (LVDS) or CONVST (CMOS) signal. Both
signals are functionally identical. The following diagrams show control with CONVST. The rising edge of
CONVST (or CSTART) starts the sample phase, if the conversion has completed and the device is in the wait
state.
Figure 2
shows the case when the device is in the conversion phase at the rising edge of CONVST. In this
case, the sample phase starts immediately at the end of the conversion phase and there is no wait state.
CONVST
BUSY
t
w1
t
w2
t
d1
t
d2
t
d3
t
d4
Wait
Sample Phase
Conversion Phase
Wait
t
acq
t
cnv
ADS8413
SLAS490–OCTOBER 2005
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
I/O
DESCRIPTION
NAME
NOT CONNECTED PINS
15
NC
–
No connection pins
Table 1. Device Configuration for Various Modes of Operation
DEVICE PINS AND RECOMMENDED LOGIC LEVELS
COMMENTS
REFERENCE FIGURES
FOR
OPERATION MODE
SAMPLING
AND
CONVERSION
FOR DATA
READ
MODE_C/D
CLK_I/E
LAT_Y/N
M1+
M1–
M2+
M2–
+VBD
AGND
AGND
+VBD
See Figures 3,4
and 5,6,8 for
more details
1
1 or 0
0
Recommended configuration
1 or 2
or M1 = 1 LVDS
or M2 = 0 LVDS
Single device
Set SYNC_I and SDI to logic 0
or + terminal to AGND and –ve
terminal to +VBD
See Figures 3,4
and 5,6,7 for
more details
0
1 or 0
0
See comments
See comments
1 or 2
Set SYNC_I and SDI to logic 0
or + terminal to AGND and –ve
terminal to +VBD
Multiple
devices
in daisy
chain
1st Device
0
1 or 0
0
See comments
See comments
1 or 2
See Figures
3,4,11 and 6,12
for more details
2nd To last
device
Maximum 4 devices supported
at 2 MSPS with 200-MHz CLK
0
0
1
See comments
See comments
1 or 2
+VBD
AGND
AGND
+VBD
1st Device
1
0
0
Multiple
devices
in
cascade
See Figures
3,4,14 and 6,15
for more details
or M1 = 1 LVDS
or M2 = 0 LVDS
(1)
Maximum 3 devices supported
at 2 MSPS
1 or 2
+VBD
AGND
AGND
+VBD
2nd To last
device
1
0
1
or M1 = 0 LVDS
or M2 = 0 LVDS
(1)
(1)
Specified polarity is suitable for a 100-
differential load across the LVDS outputs. However, polarity can be reversed to double the
output current in order to support two 100-
loads on both ends of the transmission lines, resulting in 50-
net load.
Figure 1. Sample and Convert With Wait (Less Than 2 MSPS Throughput)
9
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