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參數(shù)資料
| 型號： | ADS8411IPFBT |
| 英文描述： | 16-BIT, 2 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE |
| 中文描述： | 16位，2 MSPS的，單極輸入，微功耗采樣模數(shù)位并行接口和參考轉(zhuǎn)爐 |
| 文件頁數(shù)： | 21/23頁 |
| 文件大小： | 778K |
| 代理商： | ADS8411IPFBT |
www.ti.com
Reading Data
RESET
RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time
is 25 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In
addition, all output latches are cleared (set to zero's) after RESET. The converter goes back to normal operation
mode no later than 20 ns after RESET input is brought high.
ADS8411
SLAS369B–APRIL 2002–REVISED DECEMBER 2004
PRINCIPLES OF OPERATION (continued)
The ADS8411 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active
when CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST.
This is 50 ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be
attempted within this zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used
for multiword read operations. BYTE is used whenever lower bits of the converter result are output on the higher
byte of the bus. Refer to Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
DESCRIPTION
Full scale range
Least significant bit (LSB)
Full scale
Midscale
Midscale – 1 LSB
Zero
ANALOG VALUE
DIGITAL OUTPUT
STRAIGHT BINARY
BINARY CODE
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
V
ref
V
ref
/65536
V
ref
– 1 LSB
V
ref
/2
V
ref
/2 – 1 LSB
0 V
HEX CODE
FFFF
8000
7FFF
0000
The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB-LSB) if BYTE is low.
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15-DB8. In this
case two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on
pins DB15-DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins DB15–D8.
These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.
Table 2. Conversion Data Readout
DATA READ OUT
DB7-DB0 Pins
All one's
D7-D0
BYTE
DB15–DB8 Pins
D7–D0
D15–D8
High
Low
The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except
for the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling
edge of CS, whichever is later.
Another way to reset the device is through the use of the combination of CS and CONVST. This is useful when
the dedicated RESET pin is tied to the system reset but there is a need to abort only the conversion in a specific
converter. Since the BUSY signal is held high during the conversion, either one of these conditions triggers an
internal self-clear reset to the converter just the same as a reset via the dedicated RESET pin. The reset does
not have to be cleared as for the dedicated RESET pin. A reset can be started with either of the two following
steps.
Issue a CONVST when CS is low and a conversion is in progress. The falling edge of CONVST must satisfy
the timing as specified by the timing parameter t
su(AB)
mentioned in the timing characteristics table to ensure
a reset. The falling edge of CONVST starts a reset. Timing is the same as a reset using the dedicated
RESET pin except the instance of the falling edge is replaced by the falling edge of CONVST.
Issue a CS while a conversion is in progress. The falling edge of CS must satisfy the timing as specified by
the timing parameter t
su(AB)
mentioned in the timing characteristics table to ensure a reset.The falling edge of
CS causes a reset. Timing is the same as a reset using the dedicated RESET pin except the instance of the
falling edge is replaced by the falling edge of CS.
21
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