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參數(shù)資料
| 型號： | ADS8401 |
| 英文描述： | 16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE |
| 中文描述： | 16位，1.25 MSPS的，單極輸入，并行接口和參考微功率取樣類比，TODIGITAL轉(zhuǎn)爐 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大?。?/td> | 238K |
| 代理商： | ADS8401 |
ADS8401
SLAS376B
–
DECEMBER 2002
–
REVISED APRIL 2003
www.ti.com
21
PRINCIPLES OF OPERATION
The ADS8401 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The
architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 32 for
the application circuit for the ADS8401.
The conversion clock is generated internally. The conversion time of 610 ns is capable of sustaining a 1.25-MHz
throughput.
The analog input is provided to two input pins: +IN and
–
IN. When a conversion is initiated, the differential input on
these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected
from any internal function.
REFERENCE
The ADS8401 can operate with an external reference with a range from 2.5 V to 4.2 V. A 4.096-V internal reference
is included. When internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1
μ
F
decoupling capacitor and 1
μ
F storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM) (see Figure
33). The internal reference of the converter is double buffered. If an external reference is used, the second buffer
provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the
capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if external reference
is used.
ANALOG INPUT
When the converter enters the hold mode, the voltage difference between the +IN and
–
IN inputs is captured on the
internal capacitor array. The voltage on the
–
IN input is limited between
–
0.2 V and 0.2 V, allowing the input to reject
small signals which are common to both the +IN and
–
IN inputs. The +IN input has a range of
–
0.2 V to V
ref
+ 0.2
V. The input span (+IN
–
(
–
IN)) is limited to 0 V to V
ref
.
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source
impedance. Essentially, the current into the ADS8401 charges the internal capacitor array during the sample period.
After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage
must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition time (150 ns)
of the device. When the converter goes into the hold mode, the input impedance is greater than 1 G
.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN
and
–
IN inputs and the span (+IN
–
(
–
IN)) should be within the limits specified. Outside of these ranges, the
converter
’
s linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters
should be used.
Care should be taken to ensure that the output impedance of the sources driving +IN and
–
IN inputs are matched.
If this is not observed, the two inputs could have different setting time. This may result in offset error, gain error and
linearity error which varies with temperature and input voltage.
DIGITAL INTERFACE
Timing And Control
See the timing diagrams in the specifications section for detailed information on timing signals and their requirements.
The ADS8401 uses an internal oscillator generated clock which controls the conversion rate and in turn the
throughput of the converter. No external clock input is required.
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8401 switches from the
sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal
is important to the performance of the converter. The BUSY output is brought high after CONVST goes low. BUSY
stays high throughout the conversion process and returns low when the conversion has ended.
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| ADS8401IBPFBR | 16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE |
| ADS8401IBPFBT | 16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8401EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS8401 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS8401IBPFBR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 1.25MSPS Parallel W Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8401IBPFBRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 1.25MSPS Parallel W Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8401IBPFBT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 1.25MSPS Parallel W Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8401IBPFBTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16 Bit 1.25MSPS Parallel W Ref RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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