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參數(shù)資料
| 型號(hào)： | ADS8365IPAGR |
| 英文描述： | 16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS |
| 中文描述： | 16位，AD7691的6通道同步采樣SAR類比數(shù)位轉(zhuǎn)換器 |
| 文件頁數(shù)： | 20/33頁 |
| 文件大?。?/td> | 441K |
| 代理商： | ADS8365IPAGR |
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START OF A CONVERSION AND READING
DATA
By bringing one, two, or all three of the HOLDX
signals low, the input data of the corresponding
channel X are immediately placed in the hold mode
(5ns). The conversion of this channel X follows with
the next rising edge of clock. If it is important to
detect a hold command during a certain clock-cycle,
then the falling edge of the hold signal has to occur
at least 10ns before the rising edge of clock, as
shown in
Figure 27
, t
. The hold signal can remain
low without initiating a new conversion. The hold
signal must be high for at least 15ns (as shown in
Figure 27
, t
) before it is brought low again, and
hold must stay low for at least 20ns (
Figure 27
, t
W3
).
Once a particular hold signal goes low, further
impulses of this hold signal are ignored until the
conversion is finished or the device is reset. When
the conversion is finished (after 16 clock cycles) the
sampling switches close and sample the selected
channel. The start of the next conversion must be
delayed to allow the input capacitor of the ADS8365
to be fully charged. This delay time depends on the
driving amplifier, but should be at least 800ns.
1
2
16
17
18
19
20
1
2
CONVERSION
ACQUISITION
CLK
HOLD B
EOC
CS
RD
A0
ADS8365
SBAS362A–AUGUST 2006–REVISED SEPTEMBER 2006
The
continuously (see
Figure 28
). Therefore, HOLDA and
HOLDC
are
kept
high
acquisition time, the falling edge of HOLDB takes
place just before the rising edge of clock. One
conversion requires 20 clock cycles. Here, data are
read after the next conversion is initiated by HOLDB.
To read data from channel B, A1 is set high and A2
is low. Since A0 is low during the first reading (A2 A1
A0 = 010), data B0 are put to the output. Before the
second RD, A0 switches high (A2 A1 A0 = 011) so
that data from channel B1 are read, as shown in
Table
1
.
However,
reading
conversion or on a falling hold edge might cause a
loss in performance.
ADS8365
can
also
convert
one
channel
all
the
time.
To
gain
data
during
the
Table 1. Address Control for RD Functions
A2
0
0
0
0
1
1
A1
0
0
1
1
0
0
A0
0
1
0
1
0
1
CHANNEL TO BE READ
CH A0
CH A1
CH B0
CH B1
CH C0
CH C1
Cycle mode reads registers CH A0
to CH C1 on successive transitions
of the read line
FIFO mode
1
1
0
1
1
1
Figure 28. Timing of One Conversion Cycle
20
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADS8365IPAGRG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16B 250kSPS 6Ch Simu Sampling SAR ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8365M-EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADC CONVERTER RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS8370 | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 600-kHz, PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE AND REFERENCE |
| ADS8370EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS8370 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| ADS8370I | 制造商:BB 制造商全稱:BB 功能描述:16-BIT, 600-kHz, PSEUDO-DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH SERIAL INTERFACE AND REFERENCE |
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