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參數(shù)資料
| 型號： | ADS8344N |
| 英文描述： | 16-Bit, 8-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位，8通道串行輸出采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 278K |
| 代理商： | ADS8344N |
9
ADS8344
cally 25pF). After the capacitor has been fully charged, there
is no further input current. The rate of charge transfer from
the analog source to the converter is a function of conversion
rate.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS8344 will operate with a reference in the range of
100mV to +V
CC
. Keep in mind that the analog input is the
difference between the +IN input and the –IN input as shown
in Figure 2. For example, in the single-ended mode, a 1.25V
reference, and with the COM pin grounded, the selected input
channel (CH0 - CH7) will properly digitize a signal in the
range of 0V to 1.25V. If the COM pin is connected to 0.5V,
the input range on the selected channel is 0.5V to 1.75V.
There are several critical items concerning the reference input
and its wide voltage range. As the reference voltage is re-
duced, the analog voltage weight of each digital output code
is also reduced. This is often referred to as the LSB (least
significant bit) size and is equal to the reference voltage
divided by 65536. Any offset or gain error inherent in the
A/D converter will appear to increase, in terms of LSB size,
as the reference voltage is reduced. For example, if the offset
of a given converter is 2 LSBs with a 2.5V reference, then it
will typically be 10 LSBs with a 0.5V reference. In each case,
the actual offset of the device is the same, 76.3
μ
V.
FIGURE 2. Simplified Diagram of the Analog Input.
Converter
–
IN
+IN
CH0
CH1
CH2
CH3
A2-A0
(shown 00o
B
)
(1)
SGL/DIF
(shown HIGH)
CH4
CH5
CH6
CH7
COM
NOTE: (1) See Truth Tables, Table I
and Table II for address coding.
Likewise, the noise or uncertainty of the digitized output will
increase with lower LSB size. With a reference voltage of
500mV, the LSB size is 7.6
μ
V. This level is below the
internal noise of the device. As a result, the digital output
code will not be stable and vary around a mean value by a
number of LSBs. The distribution of output codes will be
gaussian and the noise can be reduced by simply averaging
consecutive conversion results or applying a digital filter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low noise, low ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the V
REF
input is not buffered and directly
drives the capacitor digital-to-analog converter (CDAC)
portion of the ADS8344. Typically, the input current is
13
μ
A with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
DIGITAL INTERFACE
The ADS8344 has a four-wire serial interface compatible
with several microprocessor families (note that the digital
inputs are over-voltage tolerant up to +5.5V, regardless of
+V
CC
). Figure 3 shows the typical operation of the ADS8344
digital interface.
Most microprocessors communicate using 8-bit transfers;
the ADS8344 can complete a conversion with three such
transfers, for a total of 24 clock cycles on the DCLK input,
provided the timing is as shown in Figure 3.
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer appropriately, it enters the acquisition (sample)
mode. After four more clock cycles, the control byte is
complete and the converter enters the conversion mode. At
this point, the input sample/hold goes into the hold mode.
The next sixteen clock cycles accomplish the actual A/D
conversion.
Control Byte
Also, shown in Figure 3 is the placement and order of the
control bits within the control byte. Table III and IV give
detailed information about these bits. The first bit, the “S”
bit, must always be HIGH and indicates the start of the
control byte. The ADS8344 will ignore inputs on the DIN
pin until the start bit is detected. The next three bits (A2-A0)
select the active input channel or channels of the input
multiplexer (see Tables I and II and Figure 2).
The SGL/DIF-bit controls the multiplexer input mode: ei-
ther single-ended mode, the selected input channel is refer-
enced to the COM pin. In differential mode, the two selected
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8344N/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 8-Ch Serial Output Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8344N/1KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 8-Ch Serial Output Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8344NB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 8-Ch Serial Output Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8344NB | 制造商:Texas Instruments 功能描述:IC's |
| ADS8344NB | 制造商:Texas Instruments 功能描述:16BIT ADC SERIAL O/P SMD 8344 |
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