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參數(shù)資料
| 型號(hào)： | ADS8330IRSAT |
| 英文描述： | LOW POWER, 16-BIT, 1-MHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE |
| 中文描述： | 低功耗，16位，1兆赫，單/雙單極性輸入，模擬到數(shù)字串行接口變換器 |
| 文件頁(yè)數(shù)： | 8/42頁(yè) |
| 文件大?。?/td> | 1768K |
| 代理商： | ADS8330IRSAT |
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TIMING CHARACTERISTICS
All specifications typical at –40°C to 85°C, +VA = 2.7 v, +VBD = 1.8 V (unless otherwise noted)
(1)(2)
ADS8329
ADS8330
SLAS516–DECEMBER 2006
PARAMETER
MIN
0.5
0.5
21
TYP
MAX
21
18.9
23.5
UNIT
External, 3 V
≤
+VA
≤
3.6 V
External, 2.7 V
≤
+VA
≤
3 V
Internal
Frequency, conversion clock, CCLK,
f
CCLK
= 1/2 f
SCLK
f
CCLK
MHz
22.3
t
su(CSF-EOC)
t
h(CSF-EOC)
t
wL(CONVST)
t
su(CSF-EOS)
t
h(CSF-EOS)
t
su(CSR-EOS)
t
h(CSR-EOS)
t
su(CSF-SCLK1R)
t
wL(SCLK)
t
wH(SCLK)
Setup time, falling edge of CS to EOC
Hold time, falling edge of CS to EOC
Pulse duration, CONVST low
Setup time, falling edge of CS to EOS
Hold time, falling edge of CS to EOS
Setup time, rising edge of CS to EOS
Hold time, rising edge of CS to EOS
Setup time, falling edge of CS to SCLK
Pulse duration, SCLK low
Pulse duration, SCLK high
1
0
CCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
20
20
20
20
5
8
8
t
c(SCLK)
- 5
t
c(SCLK)
- 8
t
c(SCLK)
- 8
I/O Clock only
I/O and conversion clock,
3 V
≤
+VA
≤
3.6 V
I/O and conversion clock,
2.7 V
≤
+VA < 3 V
I/O Clock, chain mode
I/O and conversion clock,
chain mode,
3 V
≤
+VA
≤
3.6 V
I/O and conversion clock,
chain mode,
2.7 V
≤
+VA < 3 V
23.8
23.8
2000
26.5
2000
23.8
t
c(SCLK)
Cycle time, SCLK
ns
23.8
2000
26.5
2000
Delay time, falling edge of SCLK to SDO
invalid
Delay time, falling edge of SCLK to SDO
valid
Delay time, falling edge of CS to SDO
valid, SDO MSB output
Setup time, SDI to falling edge of SCLK
Hold time, SDI to falling edge of SCLK
Delay time, rising edge of CS/FS to SDO
3-state
Setup time, last falling edge of SCLK
before rising edge of CS/FS
Delay time, CDI high to SDO high in
daisy chain mode
t
d(SCLKF-SDOINVALID)
10-pF Load
8
ns
t
d(SCLKF-SDOVALID)
10-pF Load
23
ns
t
d(CSF-SDOVALID)
10-pF Load
23
ns
t
su(SDI-SCLKF)
t
h(SDI-SCLKF)
8
4
ns
ns
t
d(CSR-SDOZ)
8
ns
t
su(lastSCLKF-CSR)
10
ns
t
d(SDO-CDI)
10-pF Load, chain mode
23
ns
(1)
(2)
All input signals are specified with t
r
= t
f
= 1.5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
See timing diagrams.
8
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