參數(shù)資料
型號： ADS8328IPW
英文描述： LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
中文描述： 低功耗，16位，500千赫，單/雙單極性輸入，模擬到數(shù)字串行接口變換器
文件頁數(shù)： 32/40頁
文件大?。?/td> 2759K
代理商： ADS8328IPW
www.ti.com
TheseSCLKsareoptional.
CONFIGURE
1110............
READResult
READResult
EOS
EOC
EOS
Nth
Nth
from#1
Nthfrom#1
Nthfrom#1
Nthfrom#1
Nthfrom#1
N
1thfrom#2
Nthfrom#3
N
1thfrom#2
Nthfrom#1
1101b
1101b
1
16
1
16
1
16
Cascaded
ManualTrigger/ReadWhileSampling
(UseinternalCCLK,EOC,and
polarityprogrammedasactivelow)
heldlowduringtheNtimes16bitstransfercycle.
INT
CS
CONVST
#1,
CONVST
CONVST
#2,
#3
EOC#1
(activelow)
INT
#1
(active
low)
CS
/FS#3
SCLK#1,
SCLK#2,
SCLK#3
SDO#1,
CDI#2
SDO#2,
CDI#3
SDO#3
SDI#1,
SDI#2,
SDI#3
CS
/FS#1
CS
/FS#2
SCLK#2,
t
CONV
=18CCLKs
t
SAMPLE1
=3CCLKsmin
t
=
20nsmin
d(EOS-CSF)
t
d(EOS-CSF)
=
20nsmin
t
d(CSR-EOS)
=20nsmin
t
=
20nsmin
d(CSR-EOS)
t
d(CSR-EOS)
=
20nsmin
t
d(EOS-CSF)
=20nsmin
ADS8327
ADS8328
SLAS415A–APRIL 2006–REVISED MAY 2006
Care must be given to handle the multiple CS signals when the converters are operating in chain mode. The
different chip select signals must be low for the entire data transfer (in this example 48 bits for three converters).
The first 16-bit word after the falling chip select is always the data from the chip that received the chip select
signal.
Case 1: If chip select is not toggled (CS stays low), the next 16 bits are data from the upstream converter, and
so on. This is shown in
Figure 60
. If there is no upstream converter in the chain, as converter #1 in the example,
the same data from the converter is going to be shown repeatedly.
Case 2: If the chip select is toggled during a chain mode data transfer cycle, as illustrated in
Figure 61
, the
same data from the converter is read out again and again in all three discrete 16-bit cycles. This is not a desired
result.
Figure 61. Simplified Cascade Mode Timing with Shared CONVST and Discrete CS
Figure 62
shows a slightly different scenario where CONVST is not shared by the second converter. Converters
#1 and #3 have the same CONVST signal. In this case, converter #2 simply passes previous conversion data
downstream.
32
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相關PDF資料
PDF描述
ADS8327I LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
ADS8327IB LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
ADS8327IBPW LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
ADS8327IBPWR LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
ADS8327IPW LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
相關代理商/技術參數(shù)
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ADS8328IRSAR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 2.7V-5.5V 16B 500 KSPS Ser ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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