參數(shù)資料
型號(hào)： ADS8328IBPWR
英文描述： LOW POWER, 16-BIT, 500-kHz, SINGLE/DUAL UNIPOLAR INPUT, ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL INTERFACE
中文描述： 低功耗，16位，500千赫，單/雙單極性輸入，模擬到數(shù)字串行接口變換器
文件頁(yè)數(shù)： 25/40頁(yè)
文件大?。?/td> 2759K
代理商： ADS8328IBPWR
www.ti.com
ADS8327
ADS8328
SLAS415A–APRIL 2006–REVISED MAY 2006
Deep Power-Down Mode
Deep power-down mode can be activated by writing to configuration register bit CFR_D2. When the device is in
deep power-down mode, all blocks except the interface are in powerdown. The external SCLK is blocked to the
analog block. The analog blocks no longer have bias currents and the internal oscillator is turned off. In this
mode, power dissipation falls from 5 mA to 1
μ
A in 2
μ
s. The wake-up time after a powerdown is 1
μ
s. When bit
D2 in the configuration register is set to 0, the device is in deep powerdown. Setting this bit to 1 or sending a
wake-up command can resume the converter from the deep power-down state.
Nap Mode
In nap mode the ADS8327/28 turns off biasing of the comparator and the mid-volt buffer. In this mode power
dissipation falls from 5 mA in normal mode to about 0.3 mA in 200 ns after the configuration cycle. The wake-up
(resume) time from nap power-down mode is 3 CCLKs (238 ns with a 12.6-MHz conversion clock). As soon as
the CFR_D3 bit in the control register is set to 0, the device goes into nap power-down mode, regardless of the
conversion state. Setting this bit to 1 or sending a wake-up command can resume the converter from the nap
power-down state.
Auto Nap Mode
Auto nap mode is almost identical to nap mode. The only difference is the time when the device is actually
powered down and the method to wake up the device. Configuration register bit D4 is only used to
enable/disable auto nap mode. If auto nap mode is enabled, the device turns off biasing after the conversion has
finished, which means the end of conversion activates auto nap powerdown mode. Power dissipation falls from
12 mA in normal mode to about 0.3 mA in 200 ns. A wake-up command resumes the device and turns biasing
on again in 3 CCLKs (238 ns with a 12.6-MHz conversion clock). The device can also be woken up by disabling
auto nap mode when bit D4 of the configuration register is set to 1. Any channel select command 0XXXb or the
set default mode command 1111b can also wake up the device from auto nap powerdown.
NOTE:
1. This wake-up command is the word 1011b in the command word. This command sets bits
D2 and D3 to 1 in the configuration register but not D4. But a wake-up command does
remove the device from either one of these power-down states, deep/nap/auto nap
powerdown.
2. Wake-up time is defined as the time between when the host processor tries to wake up
the converter and when a convert start can occur.
Table 2. Power-Down Mode Comparisons
TYPE OF
POWERDOWN
POWER
CONSUMPTION
ACTIVATED BY
ACTIVATION TIME
RESUME POWER BY
RESUME TIME
ENABLE
Normal operation
5 mA/3.8 mA
Deep powerdown
6 nA/2 nA
Setting CFR
100
μ
s
Woken up by command 1011b
1
μ
s
Set CFR
Woken up by command 1011b to achieve 6.6 mA
since (1.3 + 12)/2 = 6.6
Nap powerdown
0.3 mA/0.2 mA
Setting CFR
200
μ
s
3 CCLKs
Set CFR
Woken up by CONVST, any channel select
command, default command 1111b, or wake up
command 1011b.
EOC (end of
conversion)
Auto nap powerdown
200
μ
s
3 CCLKs
Set CFR
25
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ADS8328IBRSAT 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 2.7V-5.5V 16B 500 KSPS Ser ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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