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Note:olddatashown.
CONFIGURE
1110............
READResult
READResult
EOS
EOC
EOS
Nth
Nthfrom#1
Nthfrom#1
Nthfrom#1
N
1thfrom#2
Nthfrom#3
N
1thfrom#2
1101b
1101b
1..................16
1
..................16
1..................16
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Cascaded
ManualTrigger/ReadWhileSampling
(UseinternalCCLK,EOCactivelowand
activelow)
heldlowduringtheNtimes16bitstransfercycle.
INT
CS
CONVST
#1,
CONVST
#3
CONVST
#2=1
EOC#1
(activelow)
INT
#1
(active
low)
SCLK#1,
SCLK#2,
SCLK#3
SDO#1,
CDI#2
SDO#2,
CDI#3
SDO#3
SDI#1,
SDI#2,
SDI#3
CS
/FS#1
CS
/FS#2,
CS
/FS#3
t
CONV
=18CCLKs
t
SAMPLE1
=3CCLKsmin
t
d(CSR-EOS)
=20nsmin
t
d(CSR-EOS)
=20nsmin
t
d(SDO-CDI)
t
d(SDO-CDI)
ADS8327
ADS8328
SLAS415A–APRIL 2006–REVISED MAY 2006
Figure 62. Simplified Cascade Timing (Separate CONVST)
The number of SCLKs required for a serial read cycle depends on the combination of different read modes, TAG
bit, chain mode, and the way a channel is selected, i.e., auto channel select. This is listed in
Table 6
.
Table 6. Required SCLKs For Different Read Out Mode Combinations
CHAIN MODE
ENABLED CFR.D5
0
0
0
0
1
1
1
1
AUTO CHANNEL
SELECT CFR.D11
0
0
1
1
0
0
1
1
NUMBER OF SCLK PER SPI
READ
16
≥
17
16
≥
17
16
24
16
24
TAG ENABLED CFR.D1
TRAILING BITS
0
1
0
1
0
1
0
1
None
MSB is TAG bit plus zero(s)
None
TAG bit plus 7 zeros
None
TAG bit plus 7 zeros
None
TAG bit plus 7 zeros
33
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