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參數(shù)資料
| 型號： | ADS8320 |
| 英文描述： | 16-Bit, High-Speed, 2.7V to 5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位，高速，2.7V到5V微功耗采樣模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 105K |
| 代理商： | ADS8320 |
10
ADS8320
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
SMPL
t
CONV
t
CYC
t
CSD
Analog Input Sample Time
4.5
5.0
Clk Cycles
Conversion Time
16
Clk Cycles
Throughput Rate
100
kHz
CS Falling to
DCLOCK LOW
0
ns
t
SUCS
CS Falling to
DCLOCK Rising
20
ns
t
hDO
DCLOCK Falling to
Current D
OUT
Not Valid
DCLOCK Falling to Next
D
OUT
Valid
CS Rising to D
OUT
Tri-State
DCLOCK Falling to D
OUT
Enabled
5
15
ns
t
dDO
30
50
ns
t
dis
t
en
70
100
ns
20
50
ns
t
f
t
r
D
OUT
Fall Time
D
OUT
Rise Time
5
25
ns
7
25
ns
FIGURE 3. ADS8320 Basic Timing Diagrams.
TABLE I. Timing Specifications (V
CC
= 2.7V and above,
–40
°
C to +85
°
C.
DESCRIPTION
ANALOG VALUE
Full Scale Range
V
REF
Least Significant
Bit (LSB)
V
REF
/65,536
BINARY CODE
HEX CODE
Full Scale
V
REF
–1 LSB
1111 1111 1111 1111
FFFF
Midscale
V
REF
/2
1000 0000 0000 0000
8000
Midscale – 1LSB
V
REF
/2 – 1 LSB
0111 1111 1111 1111
7FFF
Zero
0V
0000 0000 0000 0000
0000
DIGITAL OUTPUT
STRAIGHT BINARY
TABLE II. Ideal Input Voltages and Output Codes.
SERIAL INTERFACE
The ADS8320 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 3 and Table I. The DCLOCK signal syn-
chronizes the data transfer with each bit being transmitted on
the falling edge of DCLOCK. Most receiving systems will
capture the bitstream on the rising edge of DCLOCK. How-
ever, if the minimum hold time for D
OUT
is acceptable, the
system can use the falling edge of DCLOCK to capture each
bit.
A falling CS signal initiates the conversion and data transfer.
The first 4.5 to 5.0 clock periods of the conversion cycle are
used to sample the input signal. After the fifth falling
DCLOCK edge, D
OUT
is enabled and will output a LOW
value for one clock period. For the next 16 DCLOCK
periods, D
OUT
will output the conversion result, most signifi-
cant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
After the most significant bit (B15) has been repeated, D
OUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
DATA FORMAT
The output data from the ADS8320 is in Straight Binary
format as shown in Table II. This table represents the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, or noise.
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS8320 to
convert at up to a 100kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS8320 scales directly with
conversion rate. Therefore, the first step to achieving the
lowest power dissipation is to find the lowest conversion
rate that will satisfy the requirements of the system.
In addition, the ADS8320 is in power down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 3). Ideally, each conversion should
occur as quickly as possible, preferably at a 2.4MHz clock
rate. This way, the converter spends the longest possible
time in the power-down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the compara-
tor. The analog section dissipates power continuously, until
the power down mode is entered.
CS/SHDN
D
OUT
DCLOCK
Complete Cycle
Power Down
Conversion
Sample
Use positive clock edge for data transfer
t
SUCS
t
CONV
t
SMPL
NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
B15
(MSB)
B14 B13 B12 B11 B10 B9
B8
B0
(LSB)
B7
B1
B6
B2
B5
B3
B4
Hi-Z
0
Hi-Z
t
CSD
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PDF描述 |
|---|---|
| ADS8320E | 16-Bit, High-Speed, 2.7V to 5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS8320EB | 16-Bit, High-Speed, 2.7V to 5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS8323 | TERMINAL |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS8320E | 制造商:Rochester Electronics LLC 功能描述: |
| ADS8320E | 制造商:Texas Instruments 功能描述:16BIT ADC DUAL SMD 8320 SOIC8 |
| ADS8320E/250 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit Hi-Sp 2.7-5V MicroPwr Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS8320E/250 | 制造商:Texas Instruments 功能描述:IC 16BIT ADC 100KSPS SMD 制造商:Texas Instruments 功能描述:IC, 16BIT ADC, 100KSPS, SMD 制造商:Texas Instruments 功能描述:IC, 16BIT ADC, 100KSPS, SMD; Resolution (Bits):16bit; Sampling Rate:100kSPS; Supply Voltage Type:Single; Supply Voltage Min:2.7V; Supply Voltage Max:5.25V; Supply Current:900A; Digital IC Case Style:MSOP; No. of Pins:8; Input ;RoHS Compliant: Yes |
| ADS8320E/250G4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit Hi-Sp 2.7-5V MicroPwr Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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