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參數(shù)資料
| 型號： | ADS828E/1KG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 10BIT 75MHZ ADC 28-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | SpeedPlus™ |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 75M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 340mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
ADS828
11
SBAS126A
FIGURE 8. Configuration Example for External Reference Operation.
FIGURE 7. Alternative Circuit to Generate CM Voltage.
includes logic functions that allows setting the analog input
swing of the ADS828 to either a 1Vp-p or 2Vp-p full-scale
range by simply tying the RSEL pin to a Low or High
potential, respectively. While operating the ADS828 in the
external reference mode, the buffer amplifiers for the REFT
and REFB are disconnected from the reference ladder.
As shown, the ADS828 has internal 50k
pull-up resistors
at the range select pin (RSEL) and reference select pin
(INT/EXT). Leaving these pins open configures the ADS828
for a 2Vp-p input range and external reference operation.
Setting the ADS828 up for internal reference mode requires
to bringing the INT/EXT pin low.
The reference buffers can be utilized to supply up to 1mA
(sink and source) to external circuitry. The resistor ladder of
the ADS828 is divided into several segments and has two
additional nodes, ByT and ByB, which are brought out for
external bypassing only (Figure 6). To ensure proper opera-
tion with any reference configurations, it is necessary to
provide solid bypassing at all reference pins in order to keep
the clock feedthrough to a minimum. All bypassing capaci-
tors should be located as close to their respective pins as
possible.
The common-mode voltage available at the CM-pin may be
used as a bias voltage to provide the appropriate offset for
the driving circuitry. However, care must be taken not to
appreciably load this node, which is not buffered and has a
high impedance. An alternative way of generating a com-
mon-mode voltage is given in Figure 7. Here, two external
precision resistors (tolerance 1% or better) are located
between the top and bottom reference pins. The common-
mode voltage, CMV, will appear at the midpoint.
EXTERNAL REFERENCE OPERATION
For even more design flexibility, the internal reference can
be disabled and an external reference voltage be used. The
utilization of an external reference may be considered for
applications requiring higher accuracy, improved tempera-
ture performance, or a wide adjustment range of the
converter’s full-scale range. Especially in multichannel
applications, the use of a common external reference has the
benefit of obtaining better matching of the full-scale range
between converters.
The external references can vary as long as the value of the
external top reference REFTEXT stays within the range of
(VS – 1.25V) and (REFB + 0.8V), and the external bottom
reference REFBEXT stays within 1.25V and (REFT – 0.8V).
See Figure 8.
DIGITAL INPUTS AND OUTPUTS
Clock Input Requirements
Clock jitter is critical to the SNR performance of high speed,
high resolution A/D converters. Clock jitter leads to aperture
jitter (tA), which adds noise to the signal being converted. The
ADS828 samples the input signal on the rising edge of the
CLK input. Therefore, this edge should have the lowest
possible jitter. The jitter noise contribution to total SNR is
REFT
+3.5V
ADS828
CMV
+2.5V
REFB
+1.5V
R
1
1.0k
R
2
1.0k
0.1
F
0.1
F
ADS828
IN
INT/EXT
REFT
ByT
GND
ByB
REFB
4 x 0.1
F || 2.2F
External Top Reference
REFT = REFB +0.8V to +3.75V
+VS
BA
RSEL
GND
+5V
External Bottom Reference
REFB = REFT –0.8V to +1.25V
V
IN
A - Short for 1Vp-p Input Range
B - Short for 2Vp-p Input Range (Default)
CMV
+2.5V
DC
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