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參數(shù)資料
| 型號： | ADS820E |
| 英文描述： | 10-Bit, 20MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 10位，20MHz的采樣模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/14頁 |
| 文件大?。?/td> | 295K |
| 代理商： | ADS820E |
10
ADS820
time-align it with the data created from the following quan-
tizer stages. This aligned data is fed into a digital error
correction circuit which can adjust the output data based on
the information found on the redundant bits. This technique
gives the ADS820 excellent differential linearity and guar-
antees no missing codes at the 10-bit level.
There is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The output data is available in
Straight Offset Binary (SOB) or Binary Two’s Complement
(BTC) format.
THE ANALOG INPUT AND INTERNAL REFERENCE
The analog input of the ADS820 can be configured in
various ways and driven with different circuits, depending
on the nature of the signal and the level of performance
desired. The ADS820 has an internal reference that sets the
full scale input range of the A/D. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full scale range of
+1.25V to +3.25V. Since each input is 2V peak-to-peak and
180
°
out of phase with the other, a 4V differential input
signal to the quantizer results. As shown in Figure 3, the
positive full scale reference (REFT) and the negative full
scale reference (REFB) are brought out for external bypass-
ing. In addition, the common-mode voltage (CM) may be
used as a reference to provide the appropriate offset for the
driving circuitry. However, care must be taken not to appre-
ciably load this reference node. For more information re-
garding external references, single-ended inputs, and
ADS820 drive circuits, refer to the applications section.
DIGITAL OUTPUT DATA
The 10-bit output data is provided at CMOS logic levels.
The standard output coding is Straight Offset Binary where
a full scale input signal corresponds to all “1’s” at the output.
This condition is met with pin 19 “LO” or Floating due to an
internal pull-down resistor. By applying a high voltage to
this pin, a Binary Two’s Complement output will be pro-
vided where the most significant bit is inverted. The digital
outputs of the ADS820 can be set to a high impedance state
by driving OE (pin 18) with a logic “HI”. Normal operation
is achieved with pin 18 “LO” or Floating due to internal
pull-down resistors. This function is provided for testability
purposes and is not meant to drive digital buses directly or
be dynamically changed during the conversion process.
+1.25V
+3.25V
2k
2k
0.1μF
0.1μF
+2.25V
REFT
REFB
CM
ADS820
To
Internal
Comparators
21
22
23
FIGURE 3. Internal Reference Structure.
CLOCK REQUIREMENTS
The CLK pin accepts a CMOS level clock input. The rising
and falling edge of the externally applied convert command
clock control the various interstage conversions in the pipe-
line. Therefore, the duty cycle of the clock should be held at
50% with low jitter and fast rise/fall times of 2ns or less. This
is especially important when digitizing a high frequency
input and operating at the maximum sample rate. Deviation
from a 50% duty cycle will effectively shorten some of the
interstage settling times, thus degrading the SNR and DNL
performance.
OUTPUT CODE
SOB
PIN 19
BTC
PIN 19
HI
DIFFERENTIAL INPUT
(1)
FLOATING or LO
+FS (IN = +3.25V, IN = +1.25V)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN = IN = +2.25V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = +1.25V, IN = +3.25V)
1111111111
1111111111
1111111110
1110000000
1100000000
1010000000
1000000001
1000000000
0111111111
0110000000
0100000000
0010000000
0000000001
0000000000
0111111111
0111111111
0111111110
0110000000
0100000000
0010000000
0000000001
0000000000
1111111111
1110000000
1100000000
1010000000
1000000001
1000000000
Note: In the single-ended input mode, +FS = +4.25V and –FS = +0.25V.
TABLE I. Coding Table for the ADS820.
APPLICATIONS
DRIVING THE ADS820
The ADS820 has a differential input with a common-mode
of +2.25V. For AC-coupled applications, the simplest way
to create this differential input is to drive the primary
winding of a transformer with a single-ended input. A
differential output is created on the secondary if the center
tap is tied to the common-mode voltage (CM) of +2.25V per
Figure 4. This transformer-coupled input arrangement pro-
FIGURE 4. AC-Coupled Single-Ended to Differential Drive
Circuit Using a Transformer.
Mini-Circuits
TT1-6-KK81
or equivalent
22
26
27
CM
IN
IN
ADS820
AC Input
Signal
22pF
22pF
0.1
μ
F
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