參數(shù)資料
型號: ADS802U
英文描述: 12-Bit, 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 12位,10MHz的采樣模擬數(shù)字轉(zhuǎn)換器
文件頁數(shù): 9/13頁
文件大?。?/td> 283K
代理商: ADS802U
9
ADS802
FIGURE 2. Pipeline A/D Architecture.
FIGURE 1. Input Track/Hold Configuration with Timing
Signals.
φ
1
φ
1
φ
2
φ
1
φ
1
φ
1
φ
1
φ
1
φ
2
φ
1
φ
2
φ
1
φ
2
IN
IN
OUT
OUT
Op Amp
Bias
V
CM
Op Amp
Bias
V
CM
C
H
C
I
C
I
C
H
Input Clock (50%)
Internal Non-overlapping Clock
THEORY OF OPERATION
The ADS802 is a high speed sampling analog-to-digital
converter with pipelining. It uses a fully differential archi-
tecture and digital error correction to guarantee 12-bit reso-
lution. The differential track/hold circuit is shown in Figure
1. The switches are controlled by an internal clock which
has a non-overlapping two phase signal,
φ
1 and
φ
2. At the
sampling time the input signal is sampled on the bottom
plates of the input capacitors. In the next clock phase,
φ
2, the
bottom plates of the input capacitors are connected together
and the feedback capacitors are switched to the op amp
output. At this time the charge redistributes between C
I
and
C
H
, completing one track/hold cycle. The differential output
is a held DC representation of the analog input at the sample
time. The track/hold circuit can also convert a single-ended
input signal into a fully differential signal for the quantizer.
The pipelined quantizer architecture has 11 stages with each
stage containing a two-bit quantizer and a two bit digital-to-
analog converter, as shown in Figure 2. Each two-bit quan-
tizer stage converts on the edge of the sub-clock, which is
twice the frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to
B1 (MSB)
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12 (LSB)
2-Bit
DAC
2-Bit
Flash
Input
T/H
Digital Delay
x2
x2
2-Bit
DAC
2-Bit
Flash
Digital Delay
2-Bit
Flash
Digital Delay
2-Bit
DAC
2-Bit
Flash
Digital Delay
x2
D
IN
IN
STAGE 1
STAGE 2
STAGE 10
STAGE 11
Σ
+
Σ
+
Σ
+
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