參數(shù)資料
型號(hào): ADS800
英文描述: 12-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER
中文描述: 12位,40MHz的采樣模擬數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 2/17頁(yè)
文件大小: 368K
代理商: ADS800
ADS800
SBAS035B
2
www.ti.com
ADS800U
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
UNITS
ELECTRICAL CHARACTERISTICS
At T
A
= +25
°
C, V
S
= +5V, Sampling Rate = 40MHz, and with a 50% duty cycle clock having a 2ns rise-and-fall time, unless otherwise noted.
ABSOLUTE MAXIMUM RATINGS
(1)
+V
....................................................................................................... +6V
Analog Input.............................................................. 0V to (+V
S
+ 300mV)
Logic Input ................................................................ 0V to (+V
+ 300mV)
Case Temperature ......................................................................... +100
°
C
Junction Temperature .................................................................... +150
°
C
Storage Temperature ..................................................................... +125
°
C
External Top Reference Voltage (REFT) .................................. +3.4V Max
External Bottom Reference Voltage (REFB).............................. +1.1V Min
NOTE: (1) Stresses above these ratings may permanently damage the device.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
Resolution
Specified Temperature Range
Operating Temperature Range
12
Bits
°
C
°
C
T
AMBIENT
T
AMBIENT
0
+70
+85
–40
ANALOG INPUT
Differential Full-Scale Input Range
Both Inputs,
180
°
Out-of-Phase
+1.25
+3.25
V
Common-Mode Voltage
Analog Input Bandwidth (–3dB)
Small-Signal
Full-Power
Input Impedance
+2.25
V
–20dBFS
(1)
Input
0dBFS Input
+25
°
C
+25
°
C
400
65
MHz
MHz
M
|| pF
1.25 || 4
DIGITAL INPUT
Logic Family
Convert Command
TTL/HCT Compatible CMOS
Falling Edge
Start Conversion
ACCURACY
(2)
Gain Error
f
S
= 2.5MHz
+25
°
C
Full
±
0.4
±
0.6
±
95
0.01
±
2.6
0.02
±
1.5
±
2.5
%
%
Gain Drift
Power-Supply Rejection of Gain
Input Offset Error
Power-Supply Rejection of Offset
ppm/
°
C
%FSR/%
%
%FSR/%
+V
S
=
±
5%
+25
°
C
Full
+25
°
C
0.15
±
3.5
0.15
+V
S
=
±
5%
CONVERSION CHARACTERISTICS
Sample Rate
Data Latency
10k
40M
Sample/s
Convert Cycle
6.5
DYNAMIC CHARACTERISTICS
Differential Linearity Error
f = 500kHz
t
H
= 13ns
(3)
+25
°
C
Full
+25
°
C
Full
+25
°
C
Full
±
0.6
±
0.8
±
0.4
±
0.5
Tested
±
1.9
±
1.0
LSB
LSB
LSB
LSB
LSB
LSB
f = 12MHz
±
1.0
No Missing Codes
Integral Linearity Error at f = 500kHz
Spurious-Free Dynamic Range (SFDR)
f = 500kHz (–1dBFS input)
t
H
= 13ns
(3)
+25
°
C
Full
+25
°
C
Full
65
60
58
55
72
66
61
61
dBFS
dBFS
dBFS
dBFS
f = 12MHz (–1dBFS input)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
DESIGNATOR
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
PRODUCT
PACKAGE-LEAD
ADS800U
SO-28
DW
–40
°
C to +85
°
C
ADS800U
ADS800U
Rails, 28
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at
www.ti.com.
PACKAGE/ORDERING INFORMATION
(1)
NOTES: (1) dBFS refers to dB below Full-Scale. (2) Percentage accuracies are referred to the internal A/D converter Full-Scale Range of 4Vp-p. (3) To assure
DNL and no missing code performance, see timing diagram footnote 2. (4) IMD is referred to the larger of the two input signals. If referred to the peak envelope
signal (
0dB), the intermodulation products will be 7dB lower. (5) No “rollover” of bits.
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