參數(shù)資料
型號: ADS7891
英文描述: CMOS Hex Schmitt Triggers 14-SO -55 to 125
中文描述: 3 MSPS的14位低功耗的SAR模數(shù)轉(zhuǎn)換器
文件頁數(shù): 21/26頁
文件大小: 329K
代理商: ADS7891
SLAS410 DECEMBER 2003
www.ti.com
21
DIGITAL INTERFACE
TIMING AND CONTROL
Refer to the SAMPLING AND CONVERSION START section and the CONVERSION ABORT section.
READING DATA
The ADS7891 outputs full parallel data in straight binary format as shown in Table 1. The parallel output is active
when CS
and RD
are both low. There is a minimal quiet sampling period requirement around the falling edge
of
CONVST
as stated in the timing requirements section. Data reads or bus three-state operations should not
be attempted within this period. Any other combination of CS
and RD
three-states the parallel output. Refer to
Table 1 for ideal output codes.
Table 1. Ideal Input Voltages and Output Codes
(1)
DESCRIPTION
Full scale
ANALOG VALUE
Vref 1 LSB
Vref/2
Vref/2 1 LSB
0 V
BINARY CODE
11 1111 1111 1111
HEX CODE
3FFF
Midscale
10 0000 0000 0000
2000
Midscale 1 LSB
01 1111 1111 1111
1FFF
Zero
(1)Full-scale range = Vref and least significant bit (LSB) = Vref/16384
The output data appears as a full 14-bit word (D13D0) on pins DB13 – DB0 (MSBLSB) if BYTE is low.
00 0000 0000 0000
0000
READING THE DATA IN BYTE MODE
The result can also be read on an 8-bit bus for convenience by using pins DB13DB6. In this case two reads
are necessary; the first as before, leaving BYTE low and reading the 8 most significant bits on pins DB13DB6,
and then bringing BYTE high. When BYTE is high, the lower bits (D5D0) followed by all zeros are on pins DB13
DB6 (refer to Table 2).
These multi-word read operations can be performed with multiple active RD signals (toggling) or with RD
tied
low for simplicity.
Table 2. Conversion Data Read Out
BYTE
DATA READ OUT
DB13 DB6
DB5 DB0
High
D5 D0, 00
All zeroes
Low
D13 D6
D5 D0
Also refer to the DATA READ and DEVICE OPERATION AND DATA READ IN BACK-TO-BACK
CONVERSION sections for more details.
Reset
Refer to the POWERDOWN/RESET section for the device reset sequence.
It is recommended to reset the device after power on. A reset can be issued once the power has reached 95%
of its final value.
PWD/RST
is an asynchronous active low input signal. A current conversion is aborted no later than 45 ns after
the converter is in the reset mode. In addition, the device outputs a 3F80 code to indicate a reset condition. The
converter returns back to normal operation mode immediately after the PWD/RST input is brought high.
Data is not valid for the first four conversions after a device reset.
Powerdown
Refer to the POWERDOWN/RESET section for the device powerdown sequence.
The device enters powerdown mode if a PWD/RST low duration is extended for more than a period of t
w7
.
The converter goes back to normal operation mode no later than a period of t
d13
after the PWD/RST input is
brought high.
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