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ELECTRICAL SPECIFICATIONS
www.ti.com ....................................................................................................................................................................................................... SLAS594 – JULY 2008
VDD = 2.7 V to 5.5 V, TA = –40°C to 125°C, fsample = 2 MSPS for VDD = 2.7 V to 4.5 V, fsample = 3 MSPS for VDD = 4.5 V to 5.5
V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input voltage span(1)
0
VDD
V
Absolute input voltage range
+IN
–0.2
VDD+0.2
V
CI
Input capacitance(2)
27
pF
IIlkg
Input leakage current
TA = 125°C
40
nA
SYSTEM PERFORMANCE
Resolution
12
Bits
ADS7883SB
12
No missing codes
Bits
ADS7883S
11
ADS7883SB
–1
±0.6
1
INL
Integral nonlinearity
LSB(3)
ADS7883S
–2
±0.75
2
ADS7883SB
–1
±0.5
1
DNL
Differential nonlinearity
LSB
ADS7883S
–2
±0.75
2
EO
Offset error(4)(5)(6)
–3
±0.2
3
LSB
EG
Gain error(5)
–3.5
±0.3
3.5
LSB
SAMPLING DYNAMICS
32-MHz SCLK, VDD = 3 V
398
422
Conversion time
ns
48-MHz SCLK, VDD = 5 V
265
281
32-MHz SCLK, VDD = 3 V
78
Acquisition time
ns
48-MHz SCLK, VDD = 5 V
52
32-MHz SCLK, VDD = 2.7 V to 4.5 V
2
Maximum throughput rate
MHz
48-MHz SCLK, VDD = 4.5 V to 5.5 V
3
Aperture delay
10
ns
DYNAMIC CHARACTERISTICS
THD
Total harmonic distortion(7)
fI = 100 kHz
–84
dB
fI = 100 kHz, ADS7883SB
69
72
SINAD
Signal-to-noise and distortion
dB
fI = 100 kHz, ADS7883S
68
70
SFDR
Spurious free dynamic range
fI = 100 kHz
86
dB
Full power bandwidth
At –3 dB
30
MHz
DIGITAL INPUT/OUTPUT
Logic family — CMOS
VDD = 2.7 V to 3.6 V
1.5
5.5
VIH
High-level input voltage
V
VDD = 3.6 V to 5.5 V
2.2
5.5
VDD = 2.7 V to 3.6 V
0.4
VIL
Low-level input voltage
V
VDD = 3.6 V to 5.5 V
0.8
VOH
High-level output voltage
At Isource = 200 A
VDD–0.2
V
VOL
Low-level output voltage
At Isink = 200 A
0.4
POWER SUPPLY REQUIREMENTS
+VDD
Supply voltage
2.7
3.3
5.5
V
(1)
Ideal input span; does not include gain or offset error
(2)
Refer to
Figure 24 for details on sampling circuit
(3)
LSB means least significant bit
(4)
Measured relative to an ideal full-scale input
(5)
Offset error and gain error ensured by characterization
(6)
First transition of 000H to 001H at (Vref/2
10)
(7)
Calculated on the first nine harmonics of the input frequency
Copyright 2008, Texas Instruments Incorporated
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