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參數(shù)資料
| 型號(hào)： | ADS7870 |
| 英文描述： | 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM |
| 中文描述： | 12位ADC，復(fù)用器，PGA和內(nèi)部基準(zhǔn)數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 24/27頁 |
| 文件大?。?/td> | 262K |
| 代理商： | ADS7870 |
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24
ADS7870
STARTING A CONVERSION USING
THE CONVERT PIN
A conversion can also be started by an active (rising) edge
on the CONVERT pin. Similar to the CNV/BSY register bit,
the conversion will start on the second falling edge of CCLK
after the Convert rising edge.
The CONVERT pin must stay high for at least two CCLK
periods. CONVERT must also be low for at least two CCLK
periods before going high. BUSY will go active one DCLK
period after the start of the conversion.
Contrary to the CNV/BSY bit in the register, the Convert pin
will abort any conversion in process and restart a new
conversion. BUSY will go low at the end of the conversion.
CS may be either high or low when the Convert pin starts a
conversion.
Figure 14 shows the timing of a conversion start using the
CONVERT pin. The double falling arrow on CCLK indi-
cates when the conversion cycle will actually start (the
second active CCLK edge after CONVERT goes active).
This example is for CCLK divider = 4. Notice that BUSY
goes active four CCLK periods later.
READ BACK MODES
There are four automatic modes available to read the A/D
conversion result from the A/D Output Registers. The RBM1
and RBM0 bits in the A/D Control Register (ADDR = 3)
control which mode is used by ADS7870.
Mode 0 (default mode) requires a separate read instruction
to retrieve the conversion result
Mode 1 provides the output most significant byte first
Mode 2 provides the output least significant byte first.
Mode 3 provides only the most significant byte
Mode 3 will not short cycle the A/D. Automatic Read Back
Mode is only triggered when starting a conversion using the
serial interface. Conversions started using the CONVERT
pin do not trigger the read back mode
The first bit of data for an automatic read back is sampled on
the first active SCLK edge of the read portion of instruction.
The remaining bits are sampled on the next inactive SCLK
edge (the first one after the first active edge). To avoid
getting one bit from one conversion and the remainder of the
byte from another conversion, a conversion should not finish
between the first active SCLK edge and the next inactive
edge.
Mode 0
Mode 0 (default operating mode) requires a read instruction
to be performed to retrieve a conversion result. MS byte first
format is achieved by performing a sixteen bit read from
ADDR = 1. LS byte first format is achieved by performing
a sixteen bit read from ADDR = 0. The most significant byte
only can be achieved by performing an eight bit read from
ADDR = 1.
To increase throughput it is possible to read the result of a
conversion while a conversion is in progress. The last
conversion to be completed prior to the first active SCLK
edge of the conversion data word (not the instruction byte)
is retrieved. This overlapping allows a sequence of start
conversion N, read conversion N – 1, start conversion N +
1, read conversion N, etc. For conversion 0, the result of
conversion –1 would need to be discarded.
Mode 1
In this mode, the serial interface configures itself to clock
out a conversion result as soon as a conversion is started.
This is useful since a read instruction is not required so eight
SCLK cycles are saved. This mode operates like an implied
sixteen bit read instruction byte for ADDR = 1 was sent to
the ADS7870 after starting the conversion
It is not necessary to wait for the end of the conversion to
start clocking out conversion results. The last completed
conversion at the sampling edge of SCLK will be read back
(whether a conversion is in progress or not.)
FIGURE 14. Timing Diagram Example of Conversion Start Using Convert Pin.
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Conversion Starts
CCLK
BUSY
CONV
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS7870EA | 12-Bit ADC, MUX, PGA and Internal Reference DATA ACQUISITION SYSTEM |
| ADS7891 | CMOS Hex Schmitt Triggers 14-SO -55 to 125 |
| ADS800E | 12-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
| ADS800 | 12-Bit, 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS7870EA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7870EA/1K | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7870EA/1KG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS7870EA/250 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 12-Bit |
| ADS7870EAG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit ADC MUX PGA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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