參數(shù)資料
型號： ADS7864YB/2KG4
廠商： Texas Instruments
文件頁數(shù)： 11/27頁
文件大?。?/td> 0K
描述： IC 12BIT 500KHZ 6CH ADC 48-TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Basics
標準包裝： 2,000
位數(shù)： 12
采樣率（每秒）： 500k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 50mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 12 個單端，雙極；6 個差分，雙極
配用： 296-30697-ND - EVAL MODULE FOR ADS7864M
www.ti.com
RESET
BUSY
Conversion
Channel A
empty
Conversion
Channel B
Conversion
Channel C
RD
t
0
t
1
t
2
t
3
reg. 5
reg. 4
reg. 2
reg. 3
reg. 1
reg. 0
empty
ch A1
ch A0
empty
ch B1
ch B0
ch A1
empty
ch A1
empty
ch C1
ch C0
ch B1
ch B0
ch A1
t
4
ADS7864
SBAS141A – SEPTEMBER 2000 – REVISED MARCH 2005
At time tB a HOLDB signal occurs. With the next
Bit 15 shows if the FIFO is empty (low) or if it
falling clock edge (tC) the ADS7864 puts channel B
contains channel information (high). Bits 12 to 14
into the loop to be converted next. As the reset signal
contain the Channel for the 12-bit data word (Bit 0 to
occurred at tA, the conversion of channel B will be
11). If the data is from channel A0, then bits 14 to 12
started with the next rising edge of the clock after tC.
are ‘000’. The Channel bit pattern is outlined in
Table 2 (Channel Truth Table).
Within the next clock cycle (tC to tF), HOLDC (tD) and
HOLDA (tE) occur. If more than one hold signals get
New data is always written into the next available
active within one clock cycle, channel A will be
register. At t0 (see Figure 32), the reset deletes all the
converted first. Therefore, as soon as the conversion
existing data. At t1 the new data of the channels A0
of channel B is done, the conversion of channel A will
and A1 are put into registers 0 and 1. On t2 the read
be initiated. After this second conversion, channel C
process of channel A0 data is finished. Therefore,
will be converted.
this data is dumped and A1 data is shifted to register
0. At t3 new data is available, this time from channel
The 16 bit output word has following structure:
B0 and B1. This data is written into the next available
3-Bit Channel
registers (register 1 and 2). The new data of channel
Valid Data
12-Bit Data Word
Information
C0 and C1 at t4 is put on top (registers 3 and 4).
Figure 32. Functionality Diagram of FIFO Registers
19
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